UINT32 CoreId;\r
VOID (*SecondaryStart)(VOID);\r
UINTN SecondaryEntryAddr;\r
+ UINTN AcknowledgedCoreId;\r
\r
ClusterId = GET_CLUSTER_ID(MpId);\r
CoreId = GET_CORE_ID(MpId);\r
// Clear Secondary cores MailBox\r
MmioWrite32 (ArmCoreInfoTable[Index].MailboxClearAddress, ArmCoreInfoTable[Index].MailboxClearValue);\r
\r
- SecondaryEntryAddr = 0;\r
- while (SecondaryEntryAddr = MmioRead32 (ArmCoreInfoTable[Index].MailboxGetAddress), SecondaryEntryAddr == 0) {\r
+ do {\r
ArmCallWFI ();\r
+\r
+ // Read the Mailbox\r
+ SecondaryEntryAddr = MmioRead32 (ArmCoreInfoTable[Index].MailboxGetAddress);\r
+\r
// Acknowledge the interrupt and send End of Interrupt signal.\r
- ArmGicAcknowledgeSgiFrom (PcdGet32(PcdGicInterruptInterfaceBase), PRIMARY_CORE_ID);\r
- }\r
+ ArmGicAcknowledgeInterrupt (PcdGet32(PcdGicDistributorBase), PcdGet32(PcdGicInterruptInterfaceBase), &AcknowledgedCoreId, NULL);\r
+ } while ((SecondaryEntryAddr == 0) && (AcknowledgedCoreId != PcdGet32 (PcdGicPrimaryCoreId)));\r
\r
// Jump to secondary core entry point.\r
SecondaryStart = (VOID (*)())SecondaryEntryAddr;\r
UINTN TemporaryRamBase;\r
UINTN TemporaryRamSize;\r
\r
+ // Check PcdGicPrimaryCoreId has been set in case the Primary Core is not the core 0 of Cluster 0\r
+ DEBUG_CODE_BEGIN();\r
+ if ((PcdGet32(PcdArmPrimaryCore) != 0) && (PcdGet32 (PcdGicPrimaryCoreId) == 0)) {\r
+ DEBUG((EFI_D_WARN,"Warning: the PCD PcdGicPrimaryCoreId does not seem to be set up for the configuration.\n"));\r
+ }\r
+ DEBUG_CODE_END();\r
+\r
CreatePpiList (&PpiListSize, &PpiList);\r
\r
// Enable the GIC Distributor\r