\r
// Adjust the Temporary Ram as the new Ppi List (Common + Platform Ppi Lists) is created at\r
// the base of the primary core stack\r
- PpiListSize = ALIGN_VALUE(PpiListSize, 0x4);\r
+ PpiListSize = ALIGN_VALUE(PpiListSize, CPU_STACK_ALIGNMENT);\r
TemporaryRamBase = (UINTN)PcdGet64 (PcdCPUCoresStackBase) + PpiListSize;\r
TemporaryRamSize = (UINTN)PcdGet32 (PcdCPUCorePrimaryStackSize) - PpiListSize;\r
\r
- // Make sure the size is 8-byte aligned. Once divided by 2, the size should be 4-byte aligned\r
- // to ensure the stack pointer is 4-byte aligned.\r
- TemporaryRamSize = TemporaryRamSize - (TemporaryRamSize & (0x8-1));\r
-\r
//\r
// Bind this information into the SEC hand-off state\r
// Note: this must be in sync with the stuff in the asm file\r
SecCoreData.TemporaryRamBase = (VOID *)TemporaryRamBase; // We run on the primary core (and so we use the first stack)\r
SecCoreData.TemporaryRamSize = TemporaryRamSize;\r
SecCoreData.PeiTemporaryRamBase = SecCoreData.TemporaryRamBase;\r
- SecCoreData.PeiTemporaryRamSize = SecCoreData.TemporaryRamSize / 2;\r
- SecCoreData.StackBase = (VOID *)ALIGN_VALUE((UINTN)(SecCoreData.TemporaryRamBase) + SecCoreData.PeiTemporaryRamSize, 0x4);\r
+ SecCoreData.PeiTemporaryRamSize = ALIGN_VALUE (SecCoreData.TemporaryRamSize / 2, CPU_STACK_ALIGNMENT);\r
+ SecCoreData.StackBase = SecCoreData.TemporaryRamBase + SecCoreData.PeiTemporaryRamSize;\r
SecCoreData.StackSize = (TemporaryRamBase + TemporaryRamSize) - (UINTN)SecCoreData.StackBase;\r
\r
// Jump to PEI core entry point\r