/** @file\r
*\r
-* Copyright (c) 2011-2012, ARM Limited. All rights reserved.\r
+* Copyright (c) 2011-2014, ARM Limited. All rights reserved.\r
*\r
* This program and the accompanying materials\r
* are licensed and made available under the terms and conditions of the BSD License\r
UINT32 CoreId;\r
VOID (*SecondaryStart)(VOID);\r
UINTN SecondaryEntryAddr;\r
+ UINTN AcknowledgeInterrupt;\r
+ UINTN InterruptId;\r
\r
ClusterId = GET_CLUSTER_ID(MpId);\r
CoreId = GET_CORE_ID(MpId);\r
SecondaryEntryAddr = MmioRead32 (ArmCoreInfoTable[Index].MailboxGetAddress);\r
\r
// Acknowledge the interrupt and send End of Interrupt signal.\r
- ArmGicAcknowledgeInterrupt (PcdGet32(PcdGicDistributorBase), PcdGet32(PcdGicInterruptInterfaceBase), NULL, NULL);\r
+ AcknowledgeInterrupt = ArmGicAcknowledgeInterrupt (PcdGet32 (PcdGicInterruptInterfaceBase), &InterruptId);\r
+ // Check if it is a valid interrupt ID\r
+ if (InterruptId < ArmGicGetMaxNumInterrupts (PcdGet32 (PcdGicDistributorBase))) {\r
+ // Got a valid SGI number hence signal End of Interrupt\r
+ ArmGicEndOfInterrupt (PcdGet32 (PcdGicInterruptInterfaceBase), AcknowledgeInterrupt);\r
+ }\r
} while (SecondaryEntryAddr == 0);\r
\r
// Jump to secondary core entry point.\r
UINTN TemporaryRamBase;\r
UINTN TemporaryRamSize;\r
\r
- // Check PcdGicPrimaryCoreId has been set in case the Primary Core is not the core 0 of Cluster 0\r
- DEBUG_CODE_BEGIN();\r
- if ((PcdGet32(PcdArmPrimaryCore) != 0) && (PcdGet32 (PcdGicPrimaryCoreId) == 0)) {\r
- DEBUG((EFI_D_WARN,"Warning: the PCD PcdGicPrimaryCoreId does not seem to be set up for the configuration.\n"));\r
- }\r
- DEBUG_CODE_END();\r
-\r
CreatePpiList (&PpiListSize, &PpiList);\r
\r
// Enable the GIC Distributor\r
// Adjust the Temporary Ram as the new Ppi List (Common + Platform Ppi Lists) is created at\r
// the base of the primary core stack\r
PpiListSize = ALIGN_VALUE(PpiListSize, 0x4);\r
- TemporaryRamBase = (UINTN)PcdGet32 (PcdCPUCoresStackBase) + PpiListSize;\r
+ TemporaryRamBase = (UINTN)PcdGet64 (PcdCPUCoresStackBase) + PpiListSize;\r
TemporaryRamSize = (UINTN)PcdGet32 (PcdCPUCorePrimaryStackSize) - PpiListSize;\r
\r
// Make sure the size is 8-byte aligned. Once divided by 2, the size should be 4-byte aligned\r
// Note also: HOBs (pei temp ram) MUST be above stack\r
//\r
SecCoreData.DataSize = sizeof(EFI_SEC_PEI_HAND_OFF);\r
- SecCoreData.BootFirmwareVolumeBase = (VOID *)(UINTN)PcdGet32 (PcdFvBaseAddress);\r
+ SecCoreData.BootFirmwareVolumeBase = (VOID *)(UINTN)PcdGet64 (PcdFvBaseAddress);\r
SecCoreData.BootFirmwareVolumeSize = PcdGet32 (PcdFvSize);\r
SecCoreData.TemporaryRamBase = (VOID *)TemporaryRamBase; // We run on the primary core (and so we use the first stack)\r
SecCoreData.TemporaryRamSize = TemporaryRamSize;\r