/** @file\r
*\r
-* Copyright (c) 2011, ARM Limited. All rights reserved.\r
+* Copyright (c) 2011-2012, ARM Limited. All rights reserved.\r
*\r
* This program and the accompanying materials\r
* are licensed and made available under the terms and conditions of the BSD License\r
*\r
**/\r
\r
-#include <Library/DebugLib.h>\r
-#include <Library/PcdLib.h>\r
-#include <Chipset/ArmV7.h>\r
-\r
#include "PrePeiCore.h"\r
\r
-extern EFI_PEI_PPI_DESCRIPTOR *gSecPpiTable;\r
-\r
VOID\r
EFIAPI\r
SecondaryMain (\r
- IN UINTN CoreId\r
+ IN UINTN MpId\r
)\r
{\r
ASSERT(FALSE);\r
)\r
{\r
EFI_SEC_PEI_HAND_OFF SecCoreData;\r
+ UINTN PpiListSize;\r
+ EFI_PEI_PPI_DESCRIPTOR *PpiList;\r
+ UINTN TemporaryRamBase;\r
+ UINTN TemporaryRamSize;\r
\r
+ CreatePpiList (&PpiListSize, &PpiList);\r
+\r
+ // Adjust the Temporary Ram as the new Ppi List (Common + Platform Ppi Lists) is created at\r
+ // the base of the primary core stack\r
+ PpiListSize = ALIGN_VALUE(PpiListSize, CPU_STACK_ALIGNMENT);\r
+ TemporaryRamBase = (UINTN)PcdGet64 (PcdCPUCoresStackBase) + PpiListSize;\r
+ TemporaryRamSize = (UINTN)PcdGet32 (PcdCPUCorePrimaryStackSize) - PpiListSize;\r
\r
//\r
// Bind this information into the SEC hand-off state\r
// Note also: HOBs (pei temp ram) MUST be above stack\r
//\r
SecCoreData.DataSize = sizeof(EFI_SEC_PEI_HAND_OFF);\r
- SecCoreData.BootFirmwareVolumeBase = (VOID *)(UINTN)PcdGet32 (PcdNormalFvBaseAddress);\r
- SecCoreData.BootFirmwareVolumeSize = PcdGet32 (PcdNormalFvSize);\r
- SecCoreData.TemporaryRamBase = (VOID *)(UINTN)PcdGet32 (PcdCPUCoresNonSecStackBase); // We consider we run on the primary core (and so we use the first stack)\r
- SecCoreData.TemporaryRamSize = (UINTN)(UINTN)PcdGet32 (PcdCPUCoresNonSecStackSize);\r
- SecCoreData.PeiTemporaryRamBase = (VOID *)((UINTN)(SecCoreData.TemporaryRamBase) + (SecCoreData.TemporaryRamSize / 2));\r
- SecCoreData.PeiTemporaryRamSize = SecCoreData.TemporaryRamSize / 2;\r
- SecCoreData.StackBase = SecCoreData.TemporaryRamBase;\r
- SecCoreData.StackSize = SecCoreData.TemporaryRamSize - SecCoreData.PeiTemporaryRamSize;\r
-\r
- // jump to pei core entry point\r
- (PeiCoreEntryPoint)(&SecCoreData, (VOID *)&gSecPpiTable);\r
+ SecCoreData.BootFirmwareVolumeBase = (VOID *)(UINTN)PcdGet64 (PcdFvBaseAddress);\r
+ SecCoreData.BootFirmwareVolumeSize = PcdGet32 (PcdFvSize);\r
+ SecCoreData.TemporaryRamBase = (VOID *)TemporaryRamBase; // We run on the primary core (and so we use the first stack)\r
+ SecCoreData.TemporaryRamSize = TemporaryRamSize;\r
+ SecCoreData.PeiTemporaryRamBase = SecCoreData.TemporaryRamBase;\r
+ SecCoreData.PeiTemporaryRamSize = ALIGN_VALUE (SecCoreData.TemporaryRamSize / 2, CPU_STACK_ALIGNMENT);\r
+ SecCoreData.StackBase = (VOID *)((UINTN)SecCoreData.TemporaryRamBase + SecCoreData.PeiTemporaryRamSize);\r
+ SecCoreData.StackSize = (TemporaryRamBase + TemporaryRamSize) - (UINTN)SecCoreData.StackBase;\r
+\r
+ // Jump to PEI core entry point\r
+ (PeiCoreEntryPoint)(&SecCoreData, PpiList);\r
}\r