The following call tree exposes a bug in the lifetime (ie. too late

[mirror_edk2.git] / ArmPlatformPkg / PrePeiCore / PrePeiCore.c

diff --git a/ArmPlatformPkg/PrePeiCore/PrePeiCore.c b/ArmPlatformPkg/PrePeiCore/PrePeiCore.c
index ececd4c763ab73ff8ec6a1b9baf8154e27ec4bd0..1abefaefd2991027ead3e89f9bdc9d90ea19c62b 100644 (file)
--- a/ArmPlatformPkg/PrePeiCore/PrePeiCore.c
+++ b/ArmPlatformPkg/PrePeiCore/PrePeiCore.c
@@ -1,15 +1,15 @@
 /** @file\r
 *  Main file supporting the transition to PEI Core in Normal World for Versatile Express\r
 *\r
-*  Copyright (c) 2011-2012, ARM Limited. All rights reserved.\r
-*  \r
-*  This program and the accompanying materials                          \r
-*  are licensed and made available under the terms and conditions of the BSD License         \r
-*  which accompanies this distribution.  The full text of the license may be found at        \r
-*  http://opensource.org/licenses/bsd-license.php                                            \r
+*  Copyright (c) 2011-2013, ARM Limited. All rights reserved.\r
 *\r
-*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     \r
-*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             \r
+*  This program and the accompanying materials\r
+*  are licensed and made available under the terms and conditions of the BSD License\r
+*  which accompanies this distribution.  The full text of the license may be found at\r
+*  http://opensource.org/licenses/bsd-license.php\r
+*\r
+*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
 *\r
 **/\r
 \r
@@ -71,14 +71,13 @@ CEntryPoint (
   IN  EFI_PEI_CORE_ENTRY_POINT  PeiCoreEntryPoint\r
   )\r
 {\r
-  //Clean Data cache\r
-  ArmCleanInvalidateDataCache ();\r
-\r
-  //Invalidate instruction cache\r
+  // Data Cache enabled on Primary core when MMU is enabled.\r
+  ArmDisableDataCache ();\r
+  // Invalidate Data cache\r
+  ArmInvalidateDataCache ();\r
+  // Invalidate instruction cache\r
   ArmInvalidateInstructionCache ();\r
-\r
-  // Enable Instruction & Data caches\r
-  ArmEnableDataCache ();\r
+  // Enable Instruction Caches on all cores.\r
   ArmEnableInstructionCache ();\r
 \r
   //\r
@@ -87,7 +86,8 @@ CEntryPoint (
   //\r
 \r
   // Write VBAR - The Exception Vector table must be aligned to its requirement\r
-  ASSERT (((UINTN)PeiVectorTable & ARM_VECTOR_TABLE_ALIGNMENT) == 0);\r
+  //TODO: Fix baseTools to ensure the Exception Vector Table is correctly aligned in AArch64\r
+  //ASSERT(((UINTN)PeiVectorTable & ARM_VECTOR_TABLE_ALIGNMENT) == 0);\r
   ArmWriteVBar ((UINTN)PeiVectorTable);\r
 \r
   //Note: The MMU will be enabled by MemoryPeim. Only the primary core will have the MMU on.\r