ArmPlatformPkg/ArmJunoDxe: Set the platform dependent FDT device path

[mirror_edk2.git] / ArmPlatformPkg / PrePeiCore / PrePeiCore.c

diff --git a/ArmPlatformPkg/PrePeiCore/PrePeiCore.c b/ArmPlatformPkg/PrePeiCore/PrePeiCore.c
index ececd4c763ab73ff8ec6a1b9baf8154e27ec4bd0..43ae40de2f245b695adfe102bbd0354f4c4bb9e4 100644 (file)
--- a/ArmPlatformPkg/PrePeiCore/PrePeiCore.c
+++ b/ArmPlatformPkg/PrePeiCore/PrePeiCore.c
@@ -1,15 +1,15 @@
 /** @file\r
 *  Main file supporting the transition to PEI Core in Normal World for Versatile Express\r
 *\r
-*  Copyright (c) 2011-2012, ARM Limited. All rights reserved.\r
-*  \r
-*  This program and the accompanying materials                          \r
-*  are licensed and made available under the terms and conditions of the BSD License         \r
-*  which accompanies this distribution.  The full text of the license may be found at        \r
-*  http://opensource.org/licenses/bsd-license.php                                            \r
+*  Copyright (c) 2011-2014, ARM Limited. All rights reserved.\r
 *\r
-*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     \r
-*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             \r
+*  This program and the accompanying materials\r
+*  are licensed and made available under the terms and conditions of the BSD License\r
+*  which accompanies this distribution.  The full text of the license may be found at\r
+*  http://opensource.org/licenses/bsd-license.php\r
+*\r
+*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
 *\r
 **/\r
 \r
@@ -53,7 +53,7 @@ CreatePpiList (
   ArmPlatformGetPlatformPpiList (&PlatformPpiListSize, &PlatformPpiList);\r
 \r
   // Copy the Common and Platform PPis in Temporrary Memory\r
-  ListBase = PcdGet32 (PcdCPUCoresStackBase);\r
+  ListBase = PcdGet64 (PcdCPUCoresStackBase);\r
   CopyMem ((VOID*)ListBase, gCommonPpiTable, sizeof(gCommonPpiTable));\r
   CopyMem ((VOID*)(ListBase + sizeof(gCommonPpiTable)), PlatformPpiList, PlatformPpiListSize);\r
 \r
@@ -71,14 +71,13 @@ CEntryPoint (
   IN  EFI_PEI_CORE_ENTRY_POINT  PeiCoreEntryPoint\r
   )\r
 {\r
-  //Clean Data cache\r
-  ArmCleanInvalidateDataCache ();\r
-\r
-  //Invalidate instruction cache\r
+  // Data Cache enabled on Primary core when MMU is enabled.\r
+  ArmDisableDataCache ();\r
+  // Invalidate Data cache\r
+  ArmInvalidateDataCache ();\r
+  // Invalidate instruction cache\r
   ArmInvalidateInstructionCache ();\r
-\r
-  // Enable Instruction & Data caches\r
-  ArmEnableDataCache ();\r
+  // Enable Instruction Caches on all cores.\r
   ArmEnableInstructionCache ();\r
 \r
   //\r
@@ -87,6 +86,8 @@ CEntryPoint (
   //\r
 \r
   // Write VBAR - The Exception Vector table must be aligned to its requirement\r
+  // Note: The AArch64 Vector table must be 2k-byte aligned - if this assertion fails ensure\r
+  // 'Align=4K' is defined into your FDF for this module.\r
   ASSERT (((UINTN)PeiVectorTable & ARM_VECTOR_TABLE_ALIGNMENT) == 0);\r
   ArmWriteVBar ((UINTN)PeiVectorTable);\r
 \r
@@ -140,7 +141,7 @@ PrePeiCoreTemporaryRamSupport (
   // Migrate the temporary memory heap to permanent memory heap.\r
   //\r
   CopyMem (NewHeap, OldHeap, CopySize >> 1);\r
-  \r
+\r
   SecSwitchStack ((UINTN)NewStack - (UINTN)OldStack);\r
 \r
   return EFI_SUCCESS;\r
@@ -153,7 +154,7 @@ PrePeiCoreGetGlobalVariableMemory (
 {\r
   ASSERT (GlobalVariableBase != NULL);\r
 \r
-  *GlobalVariableBase = (UINTN)PcdGet32 (PcdCPUCoresStackBase) +\r
+  *GlobalVariableBase = (UINTN)PcdGet64 (PcdCPUCoresStackBase) +\r
                         (UINTN)PcdGet32 (PcdCPUCorePrimaryStackSize) -\r
                         (UINTN)PcdGet32 (PcdPeiGlobalVariableSize);\r
 \r