/** @file\r
* Main file supporting the transition to PEI Core in Normal World for Versatile Express\r
*\r
-* Copyright (c) 2011, ARM Limited. All rights reserved.\r
-* \r
-* This program and the accompanying materials \r
-* are licensed and made available under the terms and conditions of the BSD License \r
-* which accompanies this distribution. The full text of the license may be found at \r
-* http://opensource.org/licenses/bsd-license.php \r
+* Copyright (c) 2011-2014, ARM Limited. All rights reserved.\r
*\r
-* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r
-* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r
+* This program and the accompanying materials\r
+* are licensed and made available under the terms and conditions of the BSD License\r
+* which accompanies this distribution. The full text of the license may be found at\r
+* http://opensource.org/licenses/bsd-license.php\r
+*\r
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
*\r
**/\r
\r
#include <Library/BaseLib.h>\r
#include <Library/DebugAgentLib.h>\r
-#include <Library/PrintLib.h>\r
#include <Library/ArmLib.h>\r
-#include <Library/SerialPortLib.h>\r
\r
#include <Ppi/ArmGlobalVariable.h>\r
-#include <Chipset/ArmV7.h>\r
\r
#include "PrePeiCore.h"\r
\r
&mTemporaryRamSupportPpi\r
},\r
{\r
- EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST,\r
+ EFI_PEI_PPI_DESCRIPTOR_PPI,\r
&gArmGlobalVariablePpiGuid,\r
&mGlobalVariablePpi\r
}\r
};\r
\r
+VOID\r
+CreatePpiList (\r
+ OUT UINTN *PpiListSize,\r
+ OUT EFI_PEI_PPI_DESCRIPTOR **PpiList\r
+ )\r
+{\r
+ EFI_PEI_PPI_DESCRIPTOR *PlatformPpiList;\r
+ UINTN PlatformPpiListSize;\r
+ UINTN ListBase;\r
+ EFI_PEI_PPI_DESCRIPTOR *LastPpi;\r
+\r
+ // Get the Platform PPIs\r
+ PlatformPpiListSize = 0;\r
+ ArmPlatformGetPlatformPpiList (&PlatformPpiListSize, &PlatformPpiList);\r
+\r
+ // Copy the Common and Platform PPis in Temporrary Memory\r
+ ListBase = PcdGet32 (PcdCPUCoresStackBase);\r
+ CopyMem ((VOID*)ListBase, gCommonPpiTable, sizeof(gCommonPpiTable));\r
+ CopyMem ((VOID*)(ListBase + sizeof(gCommonPpiTable)), PlatformPpiList, PlatformPpiListSize);\r
+\r
+ // Set the Terminate flag on the last PPI entry\r
+ LastPpi = (EFI_PEI_PPI_DESCRIPTOR*)ListBase + ((sizeof(gCommonPpiTable) + PlatformPpiListSize) / sizeof(EFI_PEI_PPI_DESCRIPTOR)) - 1;\r
+ LastPpi->Flags |= EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST;\r
+\r
+ *PpiList = (EFI_PEI_PPI_DESCRIPTOR*)ListBase;\r
+ *PpiListSize = sizeof(gCommonPpiTable) + PlatformPpiListSize;\r
+}\r
+\r
VOID\r
CEntryPoint (\r
IN UINTN MpId,\r
IN EFI_PEI_CORE_ENTRY_POINT PeiCoreEntryPoint\r
)\r
{\r
- //Clean Data cache\r
- ArmCleanInvalidateDataCache();\r
-\r
- //Invalidate instruction cache\r
- ArmInvalidateInstructionCache();\r
-\r
- // Enable Instruction & Data caches\r
- ArmEnableDataCache ();\r
+ // Data Cache enabled on Primary core when MMU is enabled.\r
+ ArmDisableDataCache ();\r
+ // Invalidate Data cache\r
+ ArmInvalidateDataCache ();\r
+ // Invalidate instruction cache\r
+ ArmInvalidateInstructionCache ();\r
+ // Enable Instruction Caches on all cores.\r
ArmEnableInstructionCache ();\r
\r
//\r
// as Non-secure interface is already enabled in Secure world.\r
//\r
\r
- // Write VBAR - The Vector table must be 32-byte aligned\r
- ASSERT(((UINT32)PeiVectorTable & ((1 << 5)-1)) == 0);\r
- ArmWriteVBar((UINT32)PeiVectorTable);\r
+ // Write VBAR - The Exception Vector table must be aligned to its requirement\r
+ // Note: The AArch64 Vector table must be 2k-byte aligned - if this assertion fails ensure\r
+ // 'Align=4K' is defined into your FDF for this module.\r
+ ASSERT (((UINTN)PeiVectorTable & ARM_VECTOR_TABLE_ALIGNMENT) == 0);\r
+ ArmWriteVBar ((UINTN)PeiVectorTable);\r
\r
//Note: The MMU will be enabled by MemoryPeim. Only the primary core will have the MMU on.\r
\r
- //If not primary Jump to Secondary Main\r
- if (IS_PRIMARY_CORE(MpId)) {\r
+ // If not primary Jump to Secondary Main\r
+ if (ArmPlatformIsPrimaryCore (MpId)) {\r
// Initialize the Debug Agent for Source Level Debugging\r
InitializeDebugAgent (DEBUG_AGENT_INIT_POSTMEM_SEC, NULL, NULL);\r
SaveAndSetDebugTimerInterrupt (TRUE);\r
\r
+ // Initialize the platform specific controllers\r
+ ArmPlatformInitialize (MpId);\r
+\r
// Goto primary Main.\r
PrimaryMain (PeiCoreEntryPoint);\r
} else {\r
// Migrate the temporary memory heap to permanent memory heap.\r
//\r
CopyMem (NewHeap, OldHeap, CopySize >> 1);\r
- \r
+\r
SecSwitchStack ((UINTN)NewStack - (UINTN)OldStack);\r
\r
return EFI_SUCCESS;\r
return EFI_SUCCESS;\r
}\r
\r
-VOID\r
-PeiCommonExceptionEntry (\r
- IN UINT32 Entry,\r
- IN UINT32 LR\r
- )\r
-{\r
- CHAR8 Buffer[100];\r
- UINTN CharCount;\r
-\r
- switch (Entry) {\r
- case 0:\r
- CharCount = AsciiSPrint (Buffer,sizeof (Buffer),"Reset Exception at 0x%X\n\r",LR);\r
- break;\r
- case 1:\r
- CharCount = AsciiSPrint (Buffer,sizeof (Buffer),"Undefined Exception at 0x%X\n\r",LR);\r
- break;\r
- case 2:\r
- CharCount = AsciiSPrint (Buffer,sizeof (Buffer),"SWI Exception at 0x%X\n\r",LR);\r
- break;\r
- case 3:\r
- CharCount = AsciiSPrint (Buffer,sizeof (Buffer),"PrefetchAbort Exception at 0x%X\n\r",LR);\r
- break;\r
- case 4:\r
- CharCount = AsciiSPrint (Buffer,sizeof (Buffer),"DataAbort Exception at 0x%X\n\r",LR);\r
- break;\r
- case 5:\r
- CharCount = AsciiSPrint (Buffer,sizeof (Buffer),"Reserved Exception at 0x%X\n\r",LR);\r
- break;\r
- case 6:\r
- CharCount = AsciiSPrint (Buffer,sizeof (Buffer),"IRQ Exception at 0x%X\n\r",LR);\r
- break;\r
- case 7:\r
- CharCount = AsciiSPrint (Buffer,sizeof (Buffer),"FIQ Exception at 0x%X\n\r",LR);\r
- break;\r
- default:\r
- CharCount = AsciiSPrint (Buffer,sizeof (Buffer),"Unknown Exception at 0x%X\n\r",LR);\r
- break;\r
- }\r
- SerialPortWrite ((UINT8 *) Buffer, CharCount);\r
- while(1);\r
-}\r
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