ArmPkg/ArmPsciResetSystemLib: Made the library only using SMC

[mirror_edk2.git] / ArmPlatformPkg / PrePeiCore / PrePeiCore.c

diff --git a/ArmPlatformPkg/PrePeiCore/PrePeiCore.c b/ArmPlatformPkg/PrePeiCore/PrePeiCore.c
index e165fd9456a151b6a5d8873183ed6e30c156f770..93d7e1c4c0b18708d1b4d8f231fc02c599615ac2 100644 (file)
--- a/ArmPlatformPkg/PrePeiCore/PrePeiCore.c
+++ b/ArmPlatformPkg/PrePeiCore/PrePeiCore.c
@@ -1,15 +1,15 @@
 /** @file\r
 *  Main file supporting the transition to PEI Core in Normal World for Versatile Express\r
 *\r
-*  Copyright (c) 2011-2012, ARM Limited. All rights reserved.\r
-*  \r
-*  This program and the accompanying materials                          \r
-*  are licensed and made available under the terms and conditions of the BSD License         \r
-*  which accompanies this distribution.  The full text of the license may be found at        \r
-*  http://opensource.org/licenses/bsd-license.php                                            \r
+*  Copyright (c) 2011-2014, ARM Limited. All rights reserved.\r
 *\r
-*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     \r
-*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             \r
+*  This program and the accompanying materials\r
+*  are licensed and made available under the terms and conditions of the BSD License\r
+*  which accompanies this distribution.  The full text of the license may be found at\r
+*  http://opensource.org/licenses/bsd-license.php\r
+*\r
+*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
 *\r
 **/\r
 \r
@@ -71,14 +71,13 @@ CEntryPoint (
   IN  EFI_PEI_CORE_ENTRY_POINT  PeiCoreEntryPoint\r
   )\r
 {\r
-  //Clean Data cache\r
-  ArmCleanInvalidateDataCache ();\r
-\r
-  //Invalidate instruction cache\r
+  // Data Cache enabled on Primary core when MMU is enabled.\r
+  ArmDisableDataCache ();\r
+  // Invalidate Data cache\r
+  ArmInvalidateDataCache ();\r
+  // Invalidate instruction cache\r
   ArmInvalidateInstructionCache ();\r
-\r
-  // Enable Instruction & Data caches\r
-  ArmEnableDataCache ();\r
+  // Enable Instruction Caches on all cores.\r
   ArmEnableInstructionCache ();\r
 \r
   //\r
@@ -87,8 +86,9 @@ CEntryPoint (
   //\r
 \r
   // Write VBAR - The Exception Vector table must be aligned to its requirement\r
-  //TODO: Fix baseTools to ensure the Exception Vector Table is correctly aligned in AArch64\r
-  //ASSERT(((UINTN)PeiVectorTable & ARM_VECTOR_TABLE_ALIGNMENT) == 0);\r
+  // Note: The AArch64 Vector table must be 2k-byte aligned - if this assertion fails ensure\r
+  // 'Align=4K' is defined into your FDF for this module.\r
+  ASSERT (((UINTN)PeiVectorTable & ARM_VECTOR_TABLE_ALIGNMENT) == 0);\r
   ArmWriteVBar ((UINTN)PeiVectorTable);\r
 \r
   //Note: The MMU will be enabled by MemoryPeim. Only the primary core will have the MMU on.\r
@@ -141,7 +141,7 @@ PrePeiCoreTemporaryRamSupport (
   // Migrate the temporary memory heap to permanent memory heap.\r
   //\r
   CopyMem (NewHeap, OldHeap, CopySize >> 1);\r
-  \r
+\r
   SecSwitchStack ((UINTN)NewStack - (UINTN)OldStack);\r
 \r
   return EFI_SUCCESS;\r