/** @file\r
-* Main file supporting the transition to PEI Core in Normal World for Versatile Express\r
-*\r
-* Copyright (c) 2011-2014, ARM Limited. All rights reserved.\r
-*\r
-* This program and the accompanying materials\r
-* are licensed and made available under the terms and conditions of the BSD License\r
-* which accompanies this distribution. The full text of the license may be found at\r
-* http://opensource.org/licenses/bsd-license.php\r
-*\r
-* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
-* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-*\r
+ Main file supporting the transition to PEI Core in Normal World for Versatile Express\r
+\r
+ Copyright (c) 2011 - 2022, ARM Limited. All rights reserved.\r
+\r
+ SPDX-License-Identifier: BSD-2-Clause-Patent\r
+\r
**/\r
\r
#include <Library/BaseLib.h>\r
+#include <Library/CacheMaintenanceLib.h>\r
#include <Library/DebugAgentLib.h>\r
#include <Library/ArmLib.h>\r
\r
-#include <Ppi/ArmGlobalVariable.h>\r
-\r
#include "PrePeiCore.h"\r
\r
-EFI_PEI_TEMPORARY_RAM_SUPPORT_PPI mTemporaryRamSupportPpi = { PrePeiCoreTemporaryRamSupport };\r
-ARM_GLOBAL_VARIABLE_PPI mGlobalVariablePpi = { PrePeiCoreGetGlobalVariableMemory };\r
+CONST EFI_PEI_TEMPORARY_RAM_SUPPORT_PPI mTemporaryRamSupportPpi = { PrePeiCoreTemporaryRamSupport };\r
\r
-EFI_PEI_PPI_DESCRIPTOR gCommonPpiTable[] = {\r
+CONST EFI_PEI_PPI_DESCRIPTOR gCommonPpiTable[] = {\r
{\r
EFI_PEI_PPI_DESCRIPTOR_PPI,\r
&gEfiTemporaryRamSupportPpiGuid,\r
- &mTemporaryRamSupportPpi\r
- },\r
- {\r
- EFI_PEI_PPI_DESCRIPTOR_PPI,\r
- &gArmGlobalVariablePpiGuid,\r
- &mGlobalVariablePpi\r
+ (VOID *)&mTemporaryRamSupportPpi\r
}\r
};\r
\r
OUT EFI_PEI_PPI_DESCRIPTOR **PpiList\r
)\r
{\r
- EFI_PEI_PPI_DESCRIPTOR *PlatformPpiList;\r
+ EFI_PEI_PPI_DESCRIPTOR *PlatformPpiList;\r
UINTN PlatformPpiListSize;\r
UINTN ListBase;\r
- EFI_PEI_PPI_DESCRIPTOR *LastPpi;\r
+ EFI_PEI_PPI_DESCRIPTOR *LastPpi;\r
\r
// Get the Platform PPIs\r
PlatformPpiListSize = 0;\r
ArmPlatformGetPlatformPpiList (&PlatformPpiListSize, &PlatformPpiList);\r
\r
- // Copy the Common and Platform PPis in Temporrary Memory\r
- ListBase = PcdGet32 (PcdCPUCoresStackBase);\r
- CopyMem ((VOID*)ListBase, gCommonPpiTable, sizeof(gCommonPpiTable));\r
- CopyMem ((VOID*)(ListBase + sizeof(gCommonPpiTable)), PlatformPpiList, PlatformPpiListSize);\r
+ // Copy the Common and Platform PPis in Temporary Memory\r
+ ListBase = PcdGet64 (PcdCPUCoresStackBase);\r
+ CopyMem ((VOID *)ListBase, gCommonPpiTable, sizeof (gCommonPpiTable));\r
+ CopyMem ((VOID *)(ListBase + sizeof (gCommonPpiTable)), PlatformPpiList, PlatformPpiListSize);\r
\r
// Set the Terminate flag on the last PPI entry\r
- LastPpi = (EFI_PEI_PPI_DESCRIPTOR*)ListBase + ((sizeof(gCommonPpiTable) + PlatformPpiListSize) / sizeof(EFI_PEI_PPI_DESCRIPTOR)) - 1;\r
+ LastPpi = (EFI_PEI_PPI_DESCRIPTOR *)ListBase + ((sizeof (gCommonPpiTable) + PlatformPpiListSize) / sizeof (EFI_PEI_PPI_DESCRIPTOR)) - 1;\r
LastPpi->Flags |= EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST;\r
\r
- *PpiList = (EFI_PEI_PPI_DESCRIPTOR*)ListBase;\r
- *PpiListSize = sizeof(gCommonPpiTable) + PlatformPpiListSize;\r
+ *PpiList = (EFI_PEI_PPI_DESCRIPTOR *)ListBase;\r
+ *PpiListSize = sizeof (gCommonPpiTable) + PlatformPpiListSize;\r
}\r
\r
VOID\r
{\r
// Data Cache enabled on Primary core when MMU is enabled.\r
ArmDisableDataCache ();\r
- // Invalidate Data cache\r
- ArmInvalidateDataCache ();\r
// Invalidate instruction cache\r
ArmInvalidateInstructionCache ();\r
// Enable Instruction Caches on all cores.\r
ArmEnableInstructionCache ();\r
\r
+ InvalidateDataCacheRange (\r
+ (VOID *)(UINTN)PcdGet64 (PcdCPUCoresStackBase),\r
+ PcdGet32 (PcdCPUCorePrimaryStackSize)\r
+ );\r
+\r
//\r
// Note: Doesn't have to Enable CPU interface in non-secure world,\r
// as Non-secure interface is already enabled in Secure world.\r
ASSERT (((UINTN)PeiVectorTable & ARM_VECTOR_TABLE_ALIGNMENT) == 0);\r
ArmWriteVBar ((UINTN)PeiVectorTable);\r
\r
- //Note: The MMU will be enabled by MemoryPeim. Only the primary core will have the MMU on.\r
+ // Enable Floating Point\r
+ if (FixedPcdGet32 (PcdVFPEnabled)) {\r
+ ArmEnableVFP ();\r
+ }\r
+\r
+ // Note: The MMU will be enabled by MemoryPeim. Only the primary core will have the MMU on.\r
\r
// If not primary Jump to Secondary Main\r
if (ArmPlatformIsPrimaryCore (MpId)) {\r
+ // Invoke "ProcessLibraryConstructorList" to have all library constructors\r
+ // called.\r
+ ProcessLibraryConstructorList ();\r
+\r
// Initialize the Debug Agent for Source Level Debugging\r
InitializeDebugAgent (DEBUG_AGENT_INIT_POSTMEM_SEC, NULL, NULL);\r
SaveAndSetDebugTimerInterrupt (TRUE);\r
EFI_STATUS\r
EFIAPI\r
PrePeiCoreTemporaryRamSupport (\r
- IN CONST EFI_PEI_SERVICES **PeiServices,\r
- IN EFI_PHYSICAL_ADDRESS TemporaryMemoryBase,\r
- IN EFI_PHYSICAL_ADDRESS PermanentMemoryBase,\r
- IN UINTN CopySize\r
+ IN CONST EFI_PEI_SERVICES **PeiServices,\r
+ IN EFI_PHYSICAL_ADDRESS TemporaryMemoryBase,\r
+ IN EFI_PHYSICAL_ADDRESS PermanentMemoryBase,\r
+ IN UINTN CopySize\r
)\r
{\r
- VOID *OldHeap;\r
- VOID *NewHeap;\r
- VOID *OldStack;\r
- VOID *NewStack;\r
+ VOID *OldHeap;\r
+ VOID *NewHeap;\r
+ VOID *OldStack;\r
+ VOID *NewStack;\r
+ UINTN HeapSize;\r
+\r
+ HeapSize = ALIGN_VALUE (CopySize / 2, CPU_STACK_ALIGNMENT);\r
\r
- OldHeap = (VOID*)(UINTN)TemporaryMemoryBase;\r
- NewHeap = (VOID*)((UINTN)PermanentMemoryBase + (CopySize >> 1));\r
+ OldHeap = (VOID *)(UINTN)TemporaryMemoryBase;\r
+ NewHeap = (VOID *)((UINTN)PermanentMemoryBase + (CopySize - HeapSize));\r
\r
- OldStack = (VOID*)((UINTN)TemporaryMemoryBase + (CopySize >> 1));\r
- NewStack = (VOID*)(UINTN)PermanentMemoryBase;\r
+ OldStack = (VOID *)((UINTN)TemporaryMemoryBase + HeapSize);\r
+ NewStack = (VOID *)(UINTN)PermanentMemoryBase;\r
\r
//\r
// Migrate the temporary memory stack to permanent memory stack.\r
//\r
- CopyMem (NewStack, OldStack, CopySize >> 1);\r
+ CopyMem (NewStack, OldStack, CopySize - HeapSize);\r
\r
//\r
// Migrate the temporary memory heap to permanent memory heap.\r
//\r
- CopyMem (NewHeap, OldHeap, CopySize >> 1);\r
- \r
- SecSwitchStack ((UINTN)NewStack - (UINTN)OldStack);\r
-\r
- return EFI_SUCCESS;\r
-}\r
-\r
-EFI_STATUS\r
-PrePeiCoreGetGlobalVariableMemory (\r
- OUT EFI_PHYSICAL_ADDRESS *GlobalVariableBase\r
- )\r
-{\r
- ASSERT (GlobalVariableBase != NULL);\r
+ CopyMem (NewHeap, OldHeap, HeapSize);\r
\r
- *GlobalVariableBase = (UINTN)PcdGet32 (PcdCPUCoresStackBase) +\r
- (UINTN)PcdGet32 (PcdCPUCorePrimaryStackSize) -\r
- (UINTN)PcdGet32 (PcdPeiGlobalVariableSize);\r
+ SecSwitchStack ((UINTN)NewStack - (UINTN)OldStack);\r
\r
return EFI_SUCCESS;\r
}\r
-\r