/** @file\r
*\r
-* Copyright (c) 2011-2012, ARM Limited. All rights reserved.\r
+* Copyright (c) 2011-2014, ARM Limited. All rights reserved.\r
*\r
-* This program and the accompanying materials\r
-* are licensed and made available under the terms and conditions of the BSD License\r
-* which accompanies this distribution. The full text of the license may be found at\r
-* http://opensource.org/licenses/bsd-license.php\r
-*\r
-* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
-* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+* SPDX-License-Identifier: BSD-2-Clause-Patent\r
*\r
**/\r
\r
\r
#include <Ppi/ArmMpCoreInfo.h>\r
\r
-EFI_STATUS\r
-GetPlatformPpi (\r
- IN EFI_GUID *PpiGuid,\r
- OUT VOID **Ppi\r
- )\r
-{\r
- UINTN PpiListSize;\r
- UINTN PpiListCount;\r
- EFI_PEI_PPI_DESCRIPTOR *PpiList;\r
- UINTN Index;\r
-\r
- PpiListSize = 0;\r
- ArmPlatformGetPlatformPpiList (&PpiListSize, &PpiList);\r
- PpiListCount = PpiListSize / sizeof(EFI_PEI_PPI_DESCRIPTOR);\r
- for (Index = 0; Index < PpiListCount; Index++, PpiList++) {\r
- if (CompareGuid (PpiList->Guid, PpiGuid) == TRUE) {\r
- *Ppi = PpiList->Ppi;\r
- return EFI_SUCCESS;\r
- }\r
- }\r
-\r
- return EFI_NOT_FOUND;\r
-}\r
-\r
VOID\r
PrimaryMain (\r
IN UINTN UefiMemoryBase,\r
IN UINTN StacksBase,\r
- IN UINTN GlobalVariableBase,\r
IN UINT64 StartTimeStamp\r
)\r
{\r
- // On MP Core Platform we must implement the ARM MP Core Info PPI (gArmMpCoreInfoPpiGuid)\r
- DEBUG_CODE_BEGIN();\r
- EFI_STATUS Status;\r
- ARM_MP_CORE_INFO_PPI *ArmMpCoreInfoPpi;\r
-\r
- Status = GetPlatformPpi (&gArmMpCoreInfoPpiGuid, (VOID**)&ArmMpCoreInfoPpi);\r
- ASSERT_EFI_ERROR (Status);\r
- DEBUG_CODE_END();\r
-\r
- // Check PcdGicPrimaryCoreId has been set in case the Primary Core is not the core 0 of Cluster 0\r
- DEBUG_CODE_BEGIN();\r
- if ((PcdGet32(PcdArmPrimaryCore) != 0) && (PcdGet32 (PcdGicPrimaryCoreId) == 0)) {\r
- DEBUG((EFI_D_WARN,"Warning: the PCD PcdGicPrimaryCoreId does not seem to be set up for the configuration.\n"));\r
- }\r
- DEBUG_CODE_END();\r
-\r
// Enable the GIC Distributor\r
- ArmGicEnableDistributor(PcdGet32(PcdGicDistributorBase));\r
+ ArmGicEnableDistributor(PcdGet64(PcdGicDistributorBase));\r
\r
- // In some cases, the secondary cores are waiting for an SGI from the next stage boot loader toresume their initialization\r
+ // In some cases, the secondary cores are waiting for an SGI from the next stage boot loader to resume their initialization\r
if (!FixedPcdGet32(PcdSendSgiToBringUpSecondaryCores)) {\r
// Sending SGI to all the Secondary CPU interfaces\r
- ArmGicSendSgiTo (PcdGet32(PcdGicDistributorBase), ARM_GIC_ICDSGIR_FILTER_EVERYONEELSE, 0x0E, PcdGet32 (PcdGicSgiIntId));\r
+ ArmGicSendSgiTo (PcdGet64(PcdGicDistributorBase), ARM_GIC_ICDSGIR_FILTER_EVERYONEELSE, 0x0E, PcdGet32 (PcdGicSgiIntId));\r
}\r
\r
- PrePiMain (UefiMemoryBase, StacksBase, GlobalVariableBase, StartTimeStamp);\r
+ PrePiMain (UefiMemoryBase, StacksBase, StartTimeStamp);\r
\r
// We must never return\r
ASSERT(FALSE);\r
UINT32 CoreId;\r
VOID (*SecondaryStart)(VOID);\r
UINTN SecondaryEntryAddr;\r
- UINTN AcknowledgedCoreId;\r
+ UINTN AcknowledgeInterrupt;\r
+ UINTN InterruptId;\r
\r
ClusterId = GET_CLUSTER_ID(MpId);\r
CoreId = GET_CORE_ID(MpId);\r
SecondaryEntryAddr = MmioRead32 (ArmCoreInfoTable[Index].MailboxGetAddress);\r
\r
// Acknowledge the interrupt and send End of Interrupt signal.\r
- ArmGicAcknowledgeInterrupt (PcdGet32(PcdGicDistributorBase), PcdGet32(PcdGicInterruptInterfaceBase), &AcknowledgedCoreId, NULL);\r
- } while ((SecondaryEntryAddr == 0) && (AcknowledgedCoreId != PcdGet32 (PcdGicPrimaryCoreId)));\r
+ AcknowledgeInterrupt = ArmGicAcknowledgeInterrupt (PcdGet64 (PcdGicInterruptInterfaceBase), &InterruptId);\r
+ // Check if it is a valid interrupt ID\r
+ if (InterruptId < ArmGicGetMaxNumInterrupts (PcdGet64 (PcdGicDistributorBase))) {\r
+ // Got a valid SGI number hence signal End of Interrupt\r
+ ArmGicEndOfInterrupt (PcdGet64 (PcdGicInterruptInterfaceBase), AcknowledgeInterrupt);\r
+ }\r
+ } while (SecondaryEntryAddr == 0);\r
\r
// Jump to secondary core entry point.\r
SecondaryStart = (VOID (*)())SecondaryEntryAddr;\r