ArmPlatformPkg/NorFlashDxe: Fixed CFI NOR Flash driver

[mirror_edk2.git] / ArmPlatformPkg / PrePi / MainMPCore.c

diff --git a/ArmPlatformPkg/PrePi/MainMPCore.c b/ArmPlatformPkg/PrePi/MainMPCore.c
index 139b60289eee749a31cb4ae3bffea919860f629b..8e61be1985b82436fca0b295f12286204ad6f818 100644 (file)
--- a/ArmPlatformPkg/PrePi/MainMPCore.c
+++ b/ArmPlatformPkg/PrePi/MainMPCore.c
@@ -15,8 +15,32 @@
 #include "PrePi.h"\r
 \r
 #include <Library/ArmGicLib.h>\r
-#include <Library/ArmMPCoreMailBoxLib.h>\r
-#include <Chipset/ArmV7.h>\r
+\r
+#include <Ppi/ArmMpCoreInfo.h>\r
+\r
+EFI_STATUS\r
+GetPlatformPpi (\r
+  IN  EFI_GUID  *PpiGuid,\r
+  OUT VOID      **Ppi\r
+  )\r
+{\r
+  UINTN                   PpiListSize;\r
+  UINTN                   PpiListCount;\r
+  EFI_PEI_PPI_DESCRIPTOR  *PpiList;\r
+  UINTN                   Index;\r
+\r
+  PpiListSize = 0;\r
+  ArmPlatformGetPlatformPpiList (&PpiListSize, &PpiList);\r
+  PpiListCount = PpiListSize / sizeof(EFI_PEI_PPI_DESCRIPTOR);\r
+  for (Index = 0; Index < PpiListCount; Index++, PpiList++) {\r
+    if (CompareGuid (PpiList->Guid, PpiGuid) == TRUE) {\r
+      *Ppi = PpiList->Ppi;\r
+      return EFI_SUCCESS;\r
+    }\r
+  }\r
+\r
+  return EFI_NOT_FOUND;\r
+}\r
 \r
 VOID\r
 PrimaryMain (\r
@@ -26,6 +50,15 @@ PrimaryMain (
   IN  UINT64                    StartTimeStamp\r
   )\r
 {\r
+  // On MP Core Platform we must implement the ARM MP Core Info PPI (gArmMpCoreInfoPpiGuid)\r
+  DEBUG_CODE_BEGIN();\r
+    EFI_STATUS              Status;\r
+    ARM_MP_CORE_INFO_PPI    *ArmMpCoreInfoPpi;\r
+\r
+    Status = GetPlatformPpi (&gArmMpCoreInfoPpiGuid, (VOID**)&ArmMpCoreInfoPpi);\r
+    ASSERT_EFI_ERROR (Status);\r
+  DEBUG_CODE_END();\r
+\r
   // Enable the GIC Distributor\r
   ArmGicEnableDistributor(PcdGet32(PcdGicDistributorBase));\r
 \r
@@ -46,23 +79,50 @@ SecondaryMain (
   IN  UINTN                     MpId\r
   )\r
 {\r
-  // Function pointer to Secondary Core entry point\r
-  VOID (*secondary_start)(VOID);\r
-  UINTN secondary_entry_addr=0;\r
+  EFI_STATUS              Status;\r
+  ARM_MP_CORE_INFO_PPI    *ArmMpCoreInfoPpi;\r
+  UINTN                   Index;\r
+  UINTN                   ArmCoreCount;\r
+  ARM_CORE_INFO           *ArmCoreInfoTable;\r
+  UINT32                  ClusterId;\r
+  UINT32                  CoreId;\r
+  VOID                    (*SecondaryStart)(VOID);\r
+  UINTN                   SecondaryEntryAddr;\r
+\r
+  ClusterId = GET_CLUSTER_ID(MpId);\r
+  CoreId    = GET_CORE_ID(MpId);\r
+\r
+  // On MP Core Platform we must implement the ARM MP Core Info PPI (gArmMpCoreInfoPpiGuid)\r
+  Status = GetPlatformPpi (&gArmMpCoreInfoPpiGuid, (VOID**)&ArmMpCoreInfoPpi);\r
+  ASSERT_EFI_ERROR (Status);\r
+\r
+  ArmCoreCount = 0;\r
+  Status = ArmMpCoreInfoPpi->GetMpCoreInfo (&ArmCoreCount, &ArmCoreInfoTable);\r
+  ASSERT_EFI_ERROR (Status);\r
+\r
+  // Find the core in the ArmCoreTable\r
+  for (Index = 0; Index < ArmCoreCount; Index++) {\r
+    if ((ArmCoreInfoTable[Index].ClusterId == ClusterId) && (ArmCoreInfoTable[Index].CoreId == CoreId)) {\r
+      break;\r
+    }\r
+  }\r
+\r
+  // The ARM Core Info Table must define every core\r
+  ASSERT (Index != ArmCoreCount);\r
 \r
   // Clear Secondary cores MailBox\r
-  ArmClearMPCoreMailbox();\r
+  MmioWrite32 (ArmCoreInfoTable[Index].MailboxClearAddress, ArmCoreInfoTable[Index].MailboxClearValue);\r
 \r
-  while (secondary_entry_addr = ArmGetMPCoreMailbox(), secondary_entry_addr == 0) {\r
-    ArmCallWFI();\r
+  SecondaryEntryAddr = 0;\r
+  while (SecondaryEntryAddr = MmioRead32 (ArmCoreInfoTable[Index].MailboxGetAddress), SecondaryEntryAddr == 0) {\r
+    ArmCallWFI ();\r
     // Acknowledge the interrupt and send End of Interrupt signal.\r
     ArmGicAcknowledgeSgiFrom (PcdGet32(PcdGicInterruptInterfaceBase), PRIMARY_CORE_ID);\r
   }\r
 \r
-  secondary_start = (VOID (*)())secondary_entry_addr;\r
-\r
   // Jump to secondary core entry point.\r
-  secondary_start();\r
+  SecondaryStart = (VOID (*)())SecondaryEntryAddr;\r
+  SecondaryStart();\r
 \r
   // The secondaries shouldn't reach here\r
   ASSERT(FALSE);\r