- For writing sin_port, htons() must be used.

[mirror_edk2.git] / ArmPlatformPkg / PrePi / MainMPCore.c

diff --git a/ArmPlatformPkg/PrePi/MainMPCore.c b/ArmPlatformPkg/PrePi/MainMPCore.c
index 139b60289eee749a31cb4ae3bffea919860f629b..998a7763f4a45fd08f1f5704e6a32da78fe9fea3 100644 (file)
--- a/ArmPlatformPkg/PrePi/MainMPCore.c
+++ b/ArmPlatformPkg/PrePi/MainMPCore.c
@@ -1,6 +1,6 @@
 /** @file\r
 *\r
-*  Copyright (c) 2011, ARM Limited. All rights reserved.\r
+*  Copyright (c) 2011-2012, ARM Limited. All rights reserved.\r
 *\r
 *  This program and the accompanying materials\r
 *  are licensed and made available under the terms and conditions of the BSD License\r
@@ -15,8 +15,8 @@
 #include "PrePi.h"\r
 \r
 #include <Library/ArmGicLib.h>\r
-#include <Library/ArmMPCoreMailBoxLib.h>\r
-#include <Chipset/ArmV7.h>\r
+\r
+#include <Ppi/ArmMpCoreInfo.h>\r
 \r
 VOID\r
 PrimaryMain (\r
@@ -26,13 +26,20 @@ PrimaryMain (
   IN  UINT64                    StartTimeStamp\r
   )\r
 {\r
+  // Check PcdGicPrimaryCoreId has been set in case the Primary Core is not the core 0 of Cluster 0\r
+  DEBUG_CODE_BEGIN();\r
+  if ((PcdGet32(PcdArmPrimaryCore) != 0) && (PcdGet32 (PcdGicPrimaryCoreId) == 0)) {\r
+    DEBUG((EFI_D_WARN,"Warning: the PCD PcdGicPrimaryCoreId does not seem to be set up for the configuration.\n"));\r
+  }\r
+  DEBUG_CODE_END();\r
+\r
   // Enable the GIC Distributor\r
   ArmGicEnableDistributor(PcdGet32(PcdGicDistributorBase));\r
 \r
-  // In some cases, the secondary cores are waiting for an SGI from the next stage boot loader toresume their initialization\r
+  // In some cases, the secondary cores are waiting for an SGI from the next stage boot loader to resume their initialization\r
   if (!FixedPcdGet32(PcdSendSgiToBringUpSecondaryCores)) {\r
     // Sending SGI to all the Secondary CPU interfaces\r
-    ArmGicSendSgiTo (PcdGet32(PcdGicDistributorBase), ARM_GIC_ICDSGIR_FILTER_EVERYONEELSE, 0x0E);\r
+    ArmGicSendSgiTo (PcdGet32(PcdGicDistributorBase), ARM_GIC_ICDSGIR_FILTER_EVERYONEELSE, 0x0E, PcdGet32 (PcdGicSgiIntId));\r
   }\r
 \r
   PrePiMain (UefiMemoryBase, StacksBase, GlobalVariableBase, StartTimeStamp);\r
@@ -46,23 +53,54 @@ SecondaryMain (
   IN  UINTN                     MpId\r
   )\r
 {\r
-  // Function pointer to Secondary Core entry point\r
-  VOID (*secondary_start)(VOID);\r
-  UINTN secondary_entry_addr=0;\r
+  EFI_STATUS              Status;\r
+  ARM_MP_CORE_INFO_PPI    *ArmMpCoreInfoPpi;\r
+  UINTN                   Index;\r
+  UINTN                   ArmCoreCount;\r
+  ARM_CORE_INFO           *ArmCoreInfoTable;\r
+  UINT32                  ClusterId;\r
+  UINT32                  CoreId;\r
+  VOID                    (*SecondaryStart)(VOID);\r
+  UINTN                   SecondaryEntryAddr;\r
+  UINTN                   AcknowledgedCoreId;\r
 \r
-  // Clear Secondary cores MailBox\r
-  ArmClearMPCoreMailbox();\r
+  ClusterId = GET_CLUSTER_ID(MpId);\r
+  CoreId    = GET_CORE_ID(MpId);\r
 \r
-  while (secondary_entry_addr = ArmGetMPCoreMailbox(), secondary_entry_addr == 0) {\r
-    ArmCallWFI();\r
-    // Acknowledge the interrupt and send End of Interrupt signal.\r
-    ArmGicAcknowledgeSgiFrom (PcdGet32(PcdGicInterruptInterfaceBase), PRIMARY_CORE_ID);\r
+  // On MP Core Platform we must implement the ARM MP Core Info PPI (gArmMpCoreInfoPpiGuid)\r
+  Status = GetPlatformPpi (&gArmMpCoreInfoPpiGuid, (VOID**)&ArmMpCoreInfoPpi);\r
+  ASSERT_EFI_ERROR (Status);\r
+\r
+  ArmCoreCount = 0;\r
+  Status = ArmMpCoreInfoPpi->GetMpCoreInfo (&ArmCoreCount, &ArmCoreInfoTable);\r
+  ASSERT_EFI_ERROR (Status);\r
+\r
+  // Find the core in the ArmCoreTable\r
+  for (Index = 0; Index < ArmCoreCount; Index++) {\r
+    if ((ArmCoreInfoTable[Index].ClusterId == ClusterId) && (ArmCoreInfoTable[Index].CoreId == CoreId)) {\r
+      break;\r
+    }\r
   }\r
 \r
-  secondary_start = (VOID (*)())secondary_entry_addr;\r
+  // The ARM Core Info Table must define every core\r
+  ASSERT (Index != ArmCoreCount);\r
+\r
+  // Clear Secondary cores MailBox\r
+  MmioWrite32 (ArmCoreInfoTable[Index].MailboxClearAddress, ArmCoreInfoTable[Index].MailboxClearValue);\r
+\r
+  do {\r
+    ArmCallWFI ();\r
+\r
+    // Read the Mailbox\r
+    SecondaryEntryAddr = MmioRead32 (ArmCoreInfoTable[Index].MailboxGetAddress);\r
+\r
+    // Acknowledge the interrupt and send End of Interrupt signal.\r
+    ArmGicAcknowledgeInterrupt (PcdGet32(PcdGicDistributorBase), PcdGet32(PcdGicInterruptInterfaceBase), &AcknowledgedCoreId, NULL);\r
+  } while ((SecondaryEntryAddr == 0) && (AcknowledgedCoreId != PcdGet32 (PcdGicPrimaryCoreId)));\r
 \r
   // Jump to secondary core entry point.\r
-  secondary_start();\r
+  SecondaryStart = (VOID (*)())SecondaryEntryAddr;\r
+  SecondaryStart();\r
 \r
   // The secondaries shouldn't reach here\r
   ASSERT(FALSE);\r