DynamicTablesPkg: SsdtSerialPortLibArm fix ECC error

[mirror_edk2.git] / ArmPlatformPkg / PrePi / PrePi.c

diff --git a/ArmPlatformPkg/PrePi/PrePi.c b/ArmPlatformPkg/PrePi/PrePi.c
index 02cff7ddc20444a12389abd2b90a3d1c528464fa..5129dd09a85ef71d2e30ecff605cf49c4e78119b 100644 (file)
--- a/ArmPlatformPkg/PrePi/PrePi.c
+++ b/ArmPlatformPkg/PrePi/PrePi.c
@@ -2,18 +2,13 @@
 *\r
 *  Copyright (c) 2011-2017, ARM Limited. All rights reserved.\r
 *\r
-*  This program and the accompanying materials\r
-*  are licensed and made available under the terms and conditions of the BSD License\r
-*  which accompanies this distribution.  The full text of the license may be found at\r
-*  http://opensource.org/licenses/bsd-license.php\r
-*\r
-*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
-*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+*  SPDX-License-Identifier: BSD-2-Clause-Patent\r
 *\r
 **/\r
 \r
 #include <PiPei.h>\r
 \r
+#include <Library/CacheMaintenanceLib.h>\r
 #include <Library/DebugAgentLib.h>\r
 #include <Library/PrePiLib.h>\r
 #include <Library/PrintLib.h>\r
@@ -28,7 +23,7 @@
 #include "PrePi.h"\r
 \r
 #define IS_XIP() (((UINT64)FixedPcdGet64 (PcdFdBaseAddress) > mSystemMemoryEnd) || \\r
-                  ((FixedPcdGet64 (PcdFdBaseAddress) + FixedPcdGet32 (PcdFdSize)) < FixedPcdGet64 (PcdSystemMemoryBase)))\r
+                  ((FixedPcdGet64 (PcdFdBaseAddress) + FixedPcdGet32 (PcdFdSize)) <= FixedPcdGet64 (PcdSystemMemoryBase)))\r
 \r
 UINT64 mSystemMemoryEnd = FixedPcdGet64(PcdSystemMemoryBase) +\r
                           FixedPcdGet64(PcdSystemMemorySize) - 1;\r
@@ -115,7 +110,7 @@ PrePiMain (
   BuildStackHob (StacksBase, StacksSize);\r
 \r
   //TODO: Call CpuPei as a library\r
-  BuildCpuHob (PcdGet8 (PcdPrePiCpuMemorySize), PcdGet8 (PcdPrePiCpuIoSize));\r
+  BuildCpuHob (ArmGetPhysicalAddressBits (), PcdGet8 (PcdPrePiCpuIoSize));\r
 \r
   if (ArmIsMpCore ()) {\r
     // Only MP Core platform need to produce gArmMpCoreInfoPpiGuid\r
@@ -184,8 +179,6 @@ CEntryPoint (
 \r
   // Data Cache enabled on Primary core when MMU is enabled.\r
   ArmDisableDataCache ();\r
-  // Invalidate Data cache\r
-  ArmInvalidateDataCache ();\r
   // Invalidate instruction cache\r
   ArmInvalidateInstructionCache ();\r
   // Enable Instruction Caches on all cores.\r
@@ -199,13 +192,17 @@ CEntryPoint (
         ArmCallSEV ();\r
       }\r
     } else {\r
-      // Wait the Primay core has defined the address of the Global Variable region (event: ARM_CPU_EVENT_DEFAULT)\r
+      // Wait the Primary core has defined the address of the Global Variable region (event: ARM_CPU_EVENT_DEFAULT)\r
       ArmCallWFE ();\r
     }\r
   }\r
 \r
   // If not primary Jump to Secondary Main\r
   if (ArmPlatformIsPrimaryCore (MpId)) {\r
+\r
+    InvalidateDataCacheRange ((VOID *)UefiMemoryBase,\r
+                              FixedPcdGet32 (PcdSystemMemoryUefiRegionSize));\r
+\r
     // Goto primary Main.\r
     PrimaryMain (UefiMemoryBase, StacksBase, StartTimeStamp);\r
   } else {\r
@@ -215,4 +212,3 @@ CEntryPoint (
   // DXE Core should always load and never return\r
   ASSERT (FALSE);\r
 }\r
-\r