Update NetLibGetMacAddress() to handle the case correctly when SNP is absent.

[mirror_edk2.git] / ArmPlatformPkg / PrePi / PrePi.c

diff --git a/ArmPlatformPkg/PrePi/PrePi.c b/ArmPlatformPkg/PrePi/PrePi.c
index c3fca90ca9826bb81679e14e1adf26f89b0224bf..7ef88c0e36a966157a51f6e8caba158f8d485fb2 100755 (executable)
--- a/ArmPlatformPkg/PrePi/PrePi.c
+++ b/ArmPlatformPkg/PrePi/PrePi.c
@@ -1,6 +1,6 @@
 /** @file\r
 *\r
-*  Copyright (c) 2011-2012, ARM Limited. All rights reserved.\r
+*  Copyright (c) 2011-2013, ARM Limited. All rights reserved.\r
 *\r
 *  This program and the accompanying materials\r
 *  are licensed and made available under the terms and conditions of the BSD License\r
@@ -111,12 +111,8 @@ PrePiMain (
           ((FixedPcdGet32 (PcdFdBaseAddress) >= FixedPcdGet32 (PcdSystemMemoryBase)) &&\r
            ((UINT32)(FixedPcdGet32 (PcdFdBaseAddress) + FixedPcdGet32 (PcdFdSize)) <= (UINT32)(FixedPcdGet32 (PcdSystemMemoryBase) + FixedPcdGet32 (PcdSystemMemorySize)))));\r
 \r
-  // Enable program flow prediction, if supported.\r
-  ArmEnableBranchPrediction ();\r
-\r
-  if (FixedPcdGet32(PcdVFPEnabled)) {\r
-    ArmEnableVFP();\r
-  }\r
+  // Initialize the architecture specific bits\r
+  ArchInitialize ();\r
 \r
   // Initialize the Serial Port\r
   SerialPortInitialize ();\r
@@ -212,10 +208,12 @@ CEntryPoint (
 {\r
   UINT64   StartTimeStamp;\r
  \r
+  ASSERT(!ArmIsMpCore() || (PcdGet32 (PcdCoreCount) > 1));\r
+\r
   // Initialize the platform specific controllers\r
   ArmPlatformInitialize (MpId);\r
 \r
-  if (IS_PRIMARY_CORE(MpId) && PerformanceMeasurementEnabled ()) {\r
+  if (ArmPlatformIsPrimaryCore (MpId) && PerformanceMeasurementEnabled ()) {\r
     // Initialize the Timer Library to setup the Timer HW controller\r
     TimerConstructor ();\r
     // We cannot call yet the PerformanceLib because the HOB List has not been initialized\r
@@ -224,21 +222,18 @@ CEntryPoint (
     StartTimeStamp = 0;\r
   }\r
 \r
-  // Clean Data cache\r
-  ArmCleanInvalidateDataCache ();\r
-\r
+  // Data Cache enabled on Primary core when MMU is enabled.\r
+  ArmDisableDataCache ();\r
+  // Invalidate Data cache\r
+  ArmInvalidateDataCache ();\r
   // Invalidate instruction cache\r
   ArmInvalidateInstructionCache ();\r
-\r
-  //TODO:Drain Write Buffer\r
-\r
-  // Enable Instruction & Data caches\r
-  ArmEnableDataCache ();\r
+  // Enable Instruction Caches on all cores.\r
   ArmEnableInstructionCache ();\r
 \r
   // Define the Global Variable region when we are not running in XIP\r
   if (!IS_XIP()) {\r
-    if (IS_PRIMARY_CORE(MpId)) {\r
+    if (ArmPlatformIsPrimaryCore (MpId)) {\r
       mGlobalVariableBase = GlobalVariableBase;\r
       if (ArmIsMpCore()) {\r
         // Signal the Global Variable Region is defined (event: ARM_CPU_EVENT_DEFAULT)\r
@@ -251,7 +246,7 @@ CEntryPoint (
   }\r
   \r
   // If not primary Jump to Secondary Main\r
-  if (IS_PRIMARY_CORE(MpId)) {\r
+  if (ArmPlatformIsPrimaryCore (MpId)) {\r
     // Goto primary Main.\r
     PrimaryMain (UefiMemoryBase, StacksBase, GlobalVariableBase, StartTimeStamp);\r
   } else {\r