ArmPlatformPkg/Sec: Remove SCR and CPTR initialization from SetupExceptionLevel3

[mirror_edk2.git] / ArmPlatformPkg / Sec / AArch64 / Helper.S

diff --git a/ArmPlatformPkg/Sec/AArch64/Helper.S b/ArmPlatformPkg/Sec/AArch64/Helper.S
index ff4625576355701365b640b3ddfac31cb10eb958..3b833bad7cfb67ac14eb2359aeaa561d6cc2a114 100644 (file)
--- a/ArmPlatformPkg/Sec/AArch64/Helper.S
+++ b/ArmPlatformPkg/Sec/AArch64/Helper.S
@@ -26,20 +26,6 @@ ASM_GLOBAL ASM_PFX(copy_cpsr_into_spsr)
 ASM_GLOBAL ASM_PFX(set_non_secure_mode)\r
 \r
 ASM_PFX(SetupExceptionLevel3):\r
-   mrs    x0, scr_el3            // Read EL3 Secure Configuration Register\r
-   orr    x0, x0, #1             // EL0 an EL1 cannot access secure memory\r
-\r
-   // Send all interrupts to their respective Exception levels for EL3\r
-   bic    x0, x0, #(1 << 1)      // IRQ\r
-   bic    x0, x0, #(1 << 2)      // FIQ\r
-   bic    x0, x0, #(1 << 3)      // Serror and Abort\r
-   orr    x0, x0, #(1 << 8)      // Enable HVC\r
-   orr    x0, x0, #(1 << 10)     // Make next level down 64Bit. This is EL2 in the case of the Model.\r
-                                 // We need a nice way to detect this.\r
-   msr    scr_el3, x0            // Write back our settings\r
-\r
-   msr    cptr_el3, xzr          // Disable copro traps to EL3\r
-\r
    // Check for the primary CPU to avoid a race on the distributor registers.\r
    mrs     x0, mpidr_el1\r
    tst     x0, #15\r