//\r
-// Copyright (c) 2011, ARM Limited. All rights reserved.\r
+// Copyright (c) 2011-2012, ARM Limited. All rights reserved.\r
// \r
// This program and the accompanying materials \r
// are licensed and made available under the terms and conditions of the BSD License \r
\r
GCC_ASM_IMPORT(CEntryPoint)\r
GCC_ASM_IMPORT(ArmPlatformSecBootAction)\r
-GCC_ASM_IMPORT(ArmPlatformInitializeBootMemory)\r
+GCC_ASM_IMPORT(ArmPlatformSecBootMemoryInit)\r
GCC_ASM_IMPORT(ArmDisableInterrupts)\r
GCC_ASM_IMPORT(ArmDisableCachesAndMmu)\r
-GCC_ASM_IMPORT(ArmWriteVBar)\r
GCC_ASM_IMPORT(ArmReadMpidr)\r
-GCC_ASM_IMPORT(SecVectorTable)\r
-GCC_ASM_IMPORT(ArmCpuSynchronizeWait)\r
+GCC_ASM_IMPORT(ArmCallWFE)\r
GCC_ASM_EXPORT(_ModuleEntryPoint)\r
\r
StartupAddr: .word ASM_PFX(CEntryPoint)\r
// Ensure that the MMU and caches are off\r
bl ASM_PFX(ArmDisableCachesAndMmu)\r
\r
+ // By default, we are doing a cold boot\r
+ mov r10, #ARM_SEC_COLD_BOOT\r
+\r
// Jump to Platform Specific Boot Action function\r
blx ASM_PFX(ArmPlatformSecBootAction)\r
\r
- // Set VBAR to the start of the exception vectors in Secure Mode\r
- LoadConstantToReg (ASM_PFX(SecVectorTable), r0)\r
- bl ASM_PFX(ArmWriteVBar)\r
-\r
_IdentifyCpu:\r
// Identify CPU ID\r
bl ASM_PFX(ArmReadMpidr)\r
and r5, r0, r1\r
\r
// Is it the Primary Core ?\r
- LoadConstantToReg (FixedPcdGet32(PcdArmPrimaryCore), r1)\r
- cmp r5, r1\r
+ LoadConstantToReg (FixedPcdGet32(PcdArmPrimaryCore), r3)\r
+ cmp r5, r3\r
// Only the primary core initialize the memory (SMC)\r
beq _InitMem\r
\r
_WaitInitMem:\r
- mov r0, #ARM_CPU_EVENT_BOOT_MEM_INIT\r
- bl ASM_PFX(ArmCpuSynchronizeWait)\r
+ // If we are not doing a cold boot in this case we should assume the Initial Memory to be already initialized\r
+ // Otherwise we have to wait the Primary Core to finish the initialization\r
+ cmp r10, #ARM_SEC_COLD_BOOT\r
+ bne _SetupSecondaryCoreStack\r
+\r
+ // Wait for the primary core to initialize the initial memory (event: BOOT_MEM_INIT)\r
+ bl ASM_PFX(ArmCallWFE)\r
// Now the Init Mem is initialized, we setup the secondary core stacks\r
b _SetupSecondaryCoreStack\r
\r
_InitMem:\r
+ // If we are not doing a cold boot in this case we should assume the Initial Memory to be already initialized\r
+ cmp r10, #ARM_SEC_COLD_BOOT\r
+ bne _SetupPrimaryCoreStack\r
+\r
// Initialize Init Boot Memory\r
- bl ASM_PFX(ArmPlatformInitializeBootMemory)\r
+ bl ASM_PFX(ArmPlatformSecBootMemoryInit)\r
\r
// Only Primary CPU could run this line (the secondary cores have jumped from _IdentifyCpu to _SetupStack)\r
LoadConstantToReg (FixedPcdGet32(PcdArmPrimaryCore), r5)\r
\r
_SetupPrimaryCoreStack:\r
- LoadConstantToReg (FixedPcdGet32(PcdCPUCoresSecStackBase), r2)\r
- LoadConstantToReg (FixedPcdGet32(PcdCPUCoreSecPrimaryStackSize), r3)\r
- // Calculate the Top of the Stack\r
- add r2, r2, r3\r
- LoadConstantToReg (FixedPcdGet32(PcdSecGlobalVariableSize), r3)\r
+ // Get the top of the primary stacks (and the base of the secondary stacks)\r
+ LoadConstantToReg (FixedPcdGet32(PcdCPUCoresSecStackBase), r1)\r
+ LoadConstantToReg (FixedPcdGet32(PcdCPUCoreSecPrimaryStackSize), r2)\r
+ add r1, r1, r2\r
+\r
+ LoadConstantToReg (FixedPcdGet32(PcdSecGlobalVariableSize), r2)\r
\r
// The reserved space for global variable must be 8-bytes aligned for pushing\r
// 64-bit variable on the stack\r
- SetPrimaryStack (r2, r3, r1)\r
-\r
- // Set all the SEC global variables to 0\r
- mov r3, sp\r
- mov r1, #0x0\r
-_InitGlobals:\r
- cmp r3, r2\r
- beq _PrepareArguments\r
- str r1, [r3], #4\r
- b _InitGlobals\r
+ SetPrimaryStack (r1, r2, r3)\r
+ b _PrepareArguments\r
\r
_SetupSecondaryCoreStack:\r
+ // Get the top of the primary stacks (and the base of the secondary stacks)\r
+ LoadConstantToReg (FixedPcdGet32(PcdCPUCoresSecStackBase), r1)\r
+ LoadConstantToReg (FixedPcdGet32(PcdCPUCoreSecPrimaryStackSize), r2)\r
+ add r1, r1, r2\r
+\r
// Get the Core Position (ClusterId * 4) + CoreId\r
- GetCorePositionInStack(r0, r5, r1)\r
+ GetCorePositionFromMpId(r0, r5, r2)\r
// The stack starts at the top of the stack region. Add '1' to the Core Position to get the top of the stack\r
add r0, r0, #1\r
\r
- // Get the base of the stack for the secondary cores\r
- LoadConstantToReg (FixedPcdGet32(PcdCPUCoresSecStackBase), r1)\r
- LoadConstantToReg (FixedPcdGet32(PcdCPUCoreSecSecondaryStackSize), r2)\r
- add r1, r1, r2\r
-\r
// StackOffset = CorePos * StackSize\r
+ LoadConstantToReg (FixedPcdGet32(PcdCPUCoreSecSecondaryStackSize), r2)\r
mul r0, r0, r2\r
// SP = StackBase + StackOffset\r
add sp, r1, r0\r
\r
-\r
_PrepareArguments:\r
// Move sec startup address into a data register\r
// Ensure we're jumping to FV version of the code (not boot remapped alias)\r
\r
// Jump to SEC C code\r
// r0 = mp_id\r
+ // r1 = Boot Mode\r
mov r0, r5\r
+ mov r1, r10\r
blx r3\r
\r
_NeverReturn:\r