/** @file\r
* Main file supporting the SEC Phase on ARM PLatforms\r
*\r
-* Copyright (c) 2011-2012, ARM Limited. All rights reserved.\r
+* Copyright (c) 2011-2013, ARM Limited. All rights reserved.\r
*\r
* This program and the accompanying materials\r
* are licensed and made available under the terms and conditions of the BSD License\r
IN INTN GicInterruptInterfaceBase\r
);\r
\r
-// Vector Table for Sec Phase\r
-VOID\r
-SecVectorTable (\r
- VOID\r
- );\r
-\r
VOID\r
enter_monitor_mode (\r
IN UINTN MonitorEntryPoint,\r
VOID\r
SecCommonExceptionEntry (\r
IN UINT32 Entry,\r
- IN UINT32 LR\r
+ IN UINTN LR\r
);\r
\r
#endif\r