BaseTools/VfrCompile/Pccts: Add virtual destructor for class DLGInputStream

[mirror_edk2.git] / BaseTools / Source / C / GenFw / Elf64Convert.c

diff --git a/BaseTools/Source/C/GenFw/Elf64Convert.c b/BaseTools/Source/C/GenFw/Elf64Convert.c
index 944c94b8f8b404dccdc1e3676c9b034f87896ef0..acf021667eab494ccf2def0d2a811a6198e25e07 100644 (file)
--- a/BaseTools/Source/C/GenFw/Elf64Convert.c
+++ b/BaseTools/Source/C/GenFw/Elf64Convert.c
@@ -1,7 +1,7 @@
 /** @file\r
 Elf64 convert solution\r
 \r
-Copyright (c) 2010 - 2014, Intel Corporation. All rights reserved.<BR>\r
+Copyright (c) 2010 - 2016, Intel Corporation. All rights reserved.<BR>\r
 Portions copyright (c) 2013-2014, ARM Ltd. All rights reserved.<BR>\r
 \r
 This program and the accompanying materials are licensed and made available\r
@@ -172,6 +172,10 @@ InitializeElf64 (
   //\r
   VerboseMsg ("Create COFF Section Offset Buffer");\r
   mCoffSectionsOffset = (UINT32 *)malloc(mEhdr->e_shnum * sizeof (UINT32));\r
+  if (mCoffSectionsOffset == NULL) {\r
+    Error (NULL, 0, 4001, "Resource", "memory cannot be allocated!");\r
+    return FALSE;\r
+  }\r
   memset(mCoffSectionsOffset, 0, mEhdr->e_shnum * sizeof(UINT32));\r
 \r
   //\r
@@ -518,6 +522,10 @@ ScanSections64 (
   // Allocate base Coff file.  Will be expanded later for relocations.\r
   //\r
   mCoffFile = (UINT8 *)malloc(mCoffOffset);\r
+  if (mCoffFile == NULL) {\r
+    Error (NULL, 0, 4001, "Resource", "memory cannot be allocated!");\r
+  }\r
+  assert (mCoffFile != NULL);\r
   memset(mCoffFile, 0, mCoffOffset);\r
 \r
   //\r
@@ -682,6 +690,20 @@ WriteSections64 (
       continue;\r
     }\r
 \r
+    //\r
+    // If this is a ET_DYN (PIE) executable, we will encounter a dynamic SHT_RELA\r
+    // section that applies to the entire binary, and which will have its section\r
+    // index set to #0 (which is a NULL section with the SHF_ALLOC bit cleared).\r
+    //\r
+    // In the absence of GOT based relocations (which we currently don't support),\r
+    // this RELA section will contain redundant R_xxx_RELATIVE relocations, one\r
+    // for every R_xxx_xx64 relocation appearing in the per-section RELA sections.\r
+    // (i.e., .rela.text and .rela.data)\r
+    //\r
+    if (RelShdr->sh_info == 0) {\r
+      continue;\r
+    }\r
+\r
     //\r
     // Relocation section found.  Now extract section information that the relocations\r
     // apply to in the ELF data and the new COFF data.\r
@@ -785,6 +807,17 @@ WriteSections64 (
             *(INT32 *)Targ = (INT32)((INT64)(*(INT32 *)Targ) - SymShdr->sh_addr + mCoffSectionsOffset[Sym->st_shndx]);\r
             VerboseMsg ("Relocation:  0x%08X", *(UINT32*)Targ);\r
             break;\r
+\r
+          case R_X86_64_PLT32:\r
+            //\r
+            // Treat R_X86_64_PLT32 relocations as R_X86_64_PC32: this is\r
+            // possible since we know all code symbol references resolve to\r
+            // definitions in the same module (UEFI has no shared libraries),\r
+            // and so there is never a reason to jump via a PLT entry,\r
+            // allowing us to resolve the reference using the symbol directly.\r
+            //\r
+            VerboseMsg ("Treating R_X86_64_PLT32 as R_X86_64_PC32 ...");\r
+            /* fall through */\r
           case R_X86_64_PC32:\r
             //\r
             // Relative relocation: Symbol - Ip + Addend\r
@@ -935,6 +968,7 @@ WriteRelocations64 (
             switch (ELF_R_TYPE(Rel->r_info)) {\r
             case R_X86_64_NONE:\r
             case R_X86_64_PC32:\r
+            case R_X86_64_PLT32:\r
               break;\r
             case R_X86_64_64:\r
               VerboseMsg ("EFI_IMAGE_REL_BASED_DIR64 Offset: 0x%08X", \r