/** @file\r
+Elf64 convert solution\r
\r
-Copyright (c) 2010 - 2011, Intel Corporation. All rights reserved.<BR>\r
+Copyright (c) 2010 - 2014, Intel Corporation. All rights reserved.<BR>\r
Portions copyright (c) 2013-2014, ARM Ltd. All rights reserved.<BR>\r
\r
This program and the accompanying materials are licensed and made available\r
//\r
// Coff information\r
//\r
-STATIC const UINT32 mCoffAlignment = 0x20;\r
+STATIC UINT32 mCoffAlignment = 0x20;\r
\r
//\r
// PE section alignment.\r
//\r
-STATIC const UINT16 mCoffNbrSections = 5;\r
+STATIC const UINT16 mCoffNbrSections = 4;\r
\r
//\r
// ELF sections to offset in Coff file.\r
STATIC UINT32 mDataOffset;\r
STATIC UINT32 mHiiRsrcOffset;\r
STATIC UINT32 mRelocOffset;\r
+STATIC UINT32 mDebugOffset;\r
\r
//\r
// Initialization Function\r
return (Offset + mCoffAlignment - 1) & ~(mCoffAlignment - 1);\r
}\r
\r
+STATIC\r
+UINT32\r
+DebugRvaAlign (\r
+ UINT32 Offset\r
+ )\r
+{\r
+ return (Offset + 3) & ~3;\r
+}\r
+\r
//\r
// filter functions\r
//\r
EFI_IMAGE_OPTIONAL_HEADER_UNION *NtHdr;\r
UINT32 CoffEntry;\r
UINT32 SectionCount;\r
- BOOLEAN FoundText;\r
+ BOOLEAN FoundSection;\r
\r
CoffEntry = 0;\r
mCoffOffset = 0;\r
- mTextOffset = 0;\r
- FoundText = FALSE;\r
\r
//\r
// Coff file start with a DOS header.\r
mTableOffset = mCoffOffset;\r
mCoffOffset += mCoffNbrSections * sizeof(EFI_IMAGE_SECTION_HEADER);\r
\r
+ //\r
+ // Set mCoffAlignment to the maximum alignment of the input sections\r
+ // we care about\r
+ //\r
+ for (i = 0; i < mEhdr->e_shnum; i++) {\r
+ Elf_Shdr *shdr = GetShdrByIndex(i);\r
+ if (shdr->sh_addralign <= mCoffAlignment) {\r
+ continue;\r
+ }\r
+ if (IsTextShdr(shdr) || IsDataShdr(shdr) || IsHiiRsrcShdr(shdr)) {\r
+ mCoffAlignment = (UINT32)shdr->sh_addralign;\r
+ }\r
+ }\r
+\r
+ //\r
+ // Move the PE/COFF header right before the first section. This will help us\r
+ // save space when converting to TE.\r
+ //\r
+ if (mCoffAlignment > mCoffOffset) {\r
+ mNtHdrOffset += mCoffAlignment - mCoffOffset;\r
+ mTableOffset += mCoffAlignment - mCoffOffset;\r
+ mCoffOffset = mCoffAlignment;\r
+ }\r
+\r
//\r
// First text sections.\r
//\r
mCoffOffset = CoffAlign(mCoffOffset);\r
+ mTextOffset = mCoffOffset;\r
+ FoundSection = FALSE;\r
SectionCount = 0;\r
for (i = 0; i < mEhdr->e_shnum; i++) {\r
Elf_Shdr *shdr = GetShdrByIndex(i);\r
if ((shdr->sh_addr & (shdr->sh_addralign - 1)) == 0) {\r
// if the section address is aligned we must align PE/COFF\r
mCoffOffset = (UINT32) ((mCoffOffset + shdr->sh_addralign - 1) & ~(shdr->sh_addralign - 1));\r
- } else if ((shdr->sh_addr % shdr->sh_addralign) != (mCoffOffset % shdr->sh_addralign)) {\r
- // ARM RVCT tools have behavior outside of the ELF specification to try\r
- // and make images smaller. If sh_addr is not aligned to sh_addralign\r
- // then the section needs to preserve sh_addr MOD sh_addralign.\r
- // Normally doing nothing here works great.\r
- Error (NULL, 0, 3000, "Invalid", "Unsupported section alignment.");\r
+ } else {\r
+ Error (NULL, 0, 3000, "Invalid", "Section address not aligned to its own alignment.");\r
}\r
}\r
\r
//\r
// Set mTextOffset with the offset of the first '.text' section\r
//\r
- if (!FoundText) {\r
+ if (!FoundSection) {\r
mTextOffset = mCoffOffset;\r
- FoundText = TRUE;\r
+ FoundSection = TRUE;\r
}\r
\r
mCoffSectionsOffset[i] = mCoffOffset;\r
}\r
}\r
\r
- if (!FoundText) {\r
+ if (!FoundSection) {\r
Error (NULL, 0, 3000, "Invalid", "Did not find any '.text' section.");\r
assert (FALSE);\r
}\r
\r
- if (mEhdr->e_machine != EM_ARM) {\r
- mCoffOffset = CoffAlign(mCoffOffset);\r
- }\r
+ mDebugOffset = DebugRvaAlign(mCoffOffset);\r
+ mCoffOffset = CoffAlign(mCoffOffset);\r
\r
if (SectionCount > 1 && mOutImageType == FW_EFI_IMAGE) {\r
Warning (NULL, 0, 0, NULL, "Mulitple sections in %s are merged into 1 text section. Source level debug might not work correctly.", mInImageName);\r
// Then data sections.\r
//\r
mDataOffset = mCoffOffset;\r
+ FoundSection = FALSE;\r
SectionCount = 0;\r
for (i = 0; i < mEhdr->e_shnum; i++) {\r
Elf_Shdr *shdr = GetShdrByIndex(i);\r
if ((shdr->sh_addr & (shdr->sh_addralign - 1)) == 0) {\r
// if the section address is aligned we must align PE/COFF\r
mCoffOffset = (UINT32) ((mCoffOffset + shdr->sh_addralign - 1) & ~(shdr->sh_addralign - 1));\r
- } else if ((shdr->sh_addr % shdr->sh_addralign) != (mCoffOffset % shdr->sh_addralign)) {\r
- // ARM RVCT tools have behavior outside of the ELF specification to try\r
- // and make images smaller. If sh_addr is not aligned to sh_addralign\r
- // then the section needs to preserve sh_addr MOD sh_addralign.\r
- // Normally doing nothing here works great.\r
- Error (NULL, 0, 3000, "Invalid", "Unsupported section alignment.");\r
+ } else {\r
+ Error (NULL, 0, 3000, "Invalid", "Section address not aligned to its own alignment.");\r
}\r
}\r
+\r
+ //\r
+ // Set mDataOffset with the offset of the first '.data' section\r
+ //\r
+ if (!FoundSection) {\r
+ mDataOffset = mCoffOffset;\r
+ FoundSection = TRUE;\r
+ }\r
mCoffSectionsOffset[i] = mCoffOffset;\r
mCoffOffset += (UINT32) shdr->sh_size;\r
SectionCount ++;\r
}\r
}\r
+\r
+ //\r
+ // Make room for .debug data in .data (or .text if .data is empty) instead of\r
+ // putting it in a section of its own. This is explicitly allowed by the\r
+ // PE/COFF spec, and prevents bloat in the binary when using large values for\r
+ // section alignment.\r
+ //\r
+ if (SectionCount > 0) {\r
+ mDebugOffset = DebugRvaAlign(mCoffOffset);\r
+ }\r
+ mCoffOffset = mDebugOffset + sizeof(EFI_IMAGE_DEBUG_DIRECTORY_ENTRY) +\r
+ sizeof(EFI_IMAGE_DEBUG_CODEVIEW_NB10_ENTRY) +\r
+ strlen(mInImageName) + 1;\r
+\r
mCoffOffset = CoffAlign(mCoffOffset);\r
+ if (SectionCount == 0) {\r
+ mDataOffset = mCoffOffset;\r
+ }\r
\r
if (SectionCount > 1 && mOutImageType == FW_EFI_IMAGE) {\r
Warning (NULL, 0, 0, NULL, "Mulitple sections in %s are merged into 1 data section. Source level debug might not work correctly.", mInImageName);\r
if ((shdr->sh_addr & (shdr->sh_addralign - 1)) == 0) {\r
// if the section address is aligned we must align PE/COFF\r
mCoffOffset = (UINT32) ((mCoffOffset + shdr->sh_addralign - 1) & ~(shdr->sh_addralign - 1));\r
- } else if ((shdr->sh_addr % shdr->sh_addralign) != (mCoffOffset % shdr->sh_addralign)) {\r
- // ARM RVCT tools have behavior outside of the ELF specification to try\r
- // and make images smaller. If sh_addr is not aligned to sh_addralign\r
- // then the section needs to preserve sh_addr MOD sh_addralign.\r
- // Normally doing nothing here works great.\r
- Error (NULL, 0, 3000, "Invalid", "Unsupported section alignment.");\r
+ } else {\r
+ Error (NULL, 0, 3000, "Invalid", "Section address not aligned to its own alignment.");\r
}\r
}\r
if (shdr->sh_size != 0) {\r
+ mHiiRsrcOffset = mCoffOffset;\r
mCoffSectionsOffset[i] = mCoffOffset;\r
mCoffOffset += (UINT32) shdr->sh_size;\r
mCoffOffset = CoffAlign(mCoffOffset);\r
}\r
} else if (mEhdr->e_machine == EM_AARCH64) {\r
\r
- // AARCH64 GCC uses RELA relocation, so all relocations have to be fixed up.\r
- // As opposed to ARM32 using REL.\r
-\r
switch (ELF_R_TYPE(Rel->r_info)) {\r
\r
- case R_AARCH64_ADR_PREL_LO21:\r
- if (Rel->r_addend != 0 ) { /* TODO */\r
- Error (NULL, 0, 3000, "Invalid", "AArch64: R_AARCH64_ADR_PREL_LO21 Need to fixup with addend!.");\r
+ case R_AARCH64_ADR_PREL_PG_HI21:\r
+ case R_AARCH64_ADD_ABS_LO12_NC:\r
+ case R_AARCH64_LDST8_ABS_LO12_NC:\r
+ case R_AARCH64_LDST16_ABS_LO12_NC:\r
+ case R_AARCH64_LDST32_ABS_LO12_NC:\r
+ case R_AARCH64_LDST64_ABS_LO12_NC:\r
+ case R_AARCH64_LDST128_ABS_LO12_NC:\r
+ //\r
+ // AArch64 PG_H21 relocations are typically paired with ABS_LO12\r
+ // relocations, where a PC-relative reference with +/- 4 GB range is\r
+ // split into a relative high part and an absolute low part. Since\r
+ // the absolute low part represents the offset into a 4 KB page, we\r
+ // have to make sure that the 4 KB relative offsets of both the\r
+ // section containing the reference as well as the section to which\r
+ // it refers have not been changed during PE/COFF conversion (i.e.,\r
+ // in ScanSections64() above).\r
+ //\r
+ if (((SecShdr->sh_addr ^ SecOffset) & 0xfff) != 0 ||\r
+ ((SymShdr->sh_addr ^ mCoffSectionsOffset[Sym->st_shndx]) & 0xfff) != 0 ||\r
+ mCoffAlignment < 0x1000) {\r
+ Error (NULL, 0, 3000, "Invalid", "WriteSections64(): %s AARCH64 small code model requires 4 KB section alignment.",\r
+ mInImageName);\r
+ break;\r
}\r
- break;\r
+ /* fall through */\r
\r
+ case R_AARCH64_ADR_PREL_LO21:\r
case R_AARCH64_CONDBR19:\r
- if (Rel->r_addend != 0 ) { /* TODO */\r
- Error (NULL, 0, 3000, "Invalid", "AArch64: R_AARCH64_CONDBR19 Need to fixup with addend!.");\r
- }\r
- break;\r
-\r
case R_AARCH64_LD_PREL_LO19:\r
- if (Rel->r_addend != 0 ) { /* TODO */\r
- Error (NULL, 0, 3000, "Invalid", "AArch64: R_AARCH64_LD_PREL_LO19 Need to fixup with addend!.");\r
- }\r
- break;\r
-\r
case R_AARCH64_CALL26:\r
- if (Rel->r_addend != 0 ) { /* TODO */\r
- Error (NULL, 0, 3000, "Invalid", "AArch64: R_AARCH64_CALL26 Need to fixup with addend!.");\r
- }\r
- break;\r
-\r
case R_AARCH64_JUMP26:\r
- if (Rel->r_addend != 0 ) { /* TODO : AArch64 '-O2' optimisation. */\r
- Error (NULL, 0, 3000, "Invalid", "AArch64: R_AARCH64_JUMP26 Need to fixup with addend!.");\r
+ case R_AARCH64_PREL64:\r
+ case R_AARCH64_PREL32:\r
+ case R_AARCH64_PREL16:\r
+ //\r
+ // The GCC toolchains (i.e., binutils) may corrupt section relative\r
+ // relocations when emitting relocation sections into fully linked\r
+ // binaries. More specifically, they tend to fail to take into\r
+ // account the fact that a '.rodata + XXX' relocation needs to have\r
+ // its addend recalculated once .rodata is merged into the .text\r
+ // section, and the relocation emitted into the .rela.text section.\r
+ //\r
+ // We cannot really recover from this loss of information, so the\r
+ // only workaround is to prevent having to recalculate any relative\r
+ // relocations at all, by using a linker script that ensures that\r
+ // the offset between the Place and the Symbol is the same in both\r
+ // the ELF and the PE/COFF versions of the binary.\r
+ //\r
+ if ((SymShdr->sh_addr - SecShdr->sh_addr) !=\r
+ (mCoffSectionsOffset[Sym->st_shndx] - SecOffset)) {\r
+ Error (NULL, 0, 3000, "Invalid", "WriteSections64(): %s AARCH64 relative relocations require identical ELF and PE/COFF section offsets",\r
+ mInImageName);\r
}\r
break;\r
\r
- case R_AARCH64_ADR_PREL_PG_HI21:\r
- // TODO : AArch64 'small' memory model.\r
- Error (NULL, 0, 3000, "Invalid", "WriteSections64(): %s unsupported ELF EM_AARCH64 relocation R_AARCH64_ADR_PREL_PG_HI21.", mInImageName);\r
- break;\r
-\r
- case R_AARCH64_ADD_ABS_LO12_NC:\r
- // TODO : AArch64 'small' memory model.\r
- Error (NULL, 0, 3000, "Invalid", "WriteSections64(): %s unsupported ELF EM_AARCH64 relocation R_AARCH64_ADD_ABS_LO12_NC.", mInImageName);\r
- break;\r
-\r
// Absolute relocations.\r
case R_AARCH64_ABS64:\r
*(UINT64 *)Targ = *(UINT64 *)Targ - SymShdr->sh_addr + mCoffSectionsOffset[Sym->st_shndx];\r
Error (NULL, 0, 3000, "Invalid", "%s unsupported ELF EM_X86_64 relocation 0x%x.", mInImageName, (unsigned) ELF_R_TYPE(Rel->r_info));\r
}\r
} else if (mEhdr->e_machine == EM_AARCH64) {\r
- // AArch64 GCC uses RELA relocation, so all relocations has to be fixed up. ARM32 uses REL.\r
+\r
switch (ELF_R_TYPE(Rel->r_info)) {\r
case R_AARCH64_ADR_PREL_LO21:\r
- break;\r
-\r
case R_AARCH64_CONDBR19:\r
- break;\r
-\r
case R_AARCH64_LD_PREL_LO19:\r
- break;\r
-\r
case R_AARCH64_CALL26:\r
- break;\r
-\r
case R_AARCH64_JUMP26:\r
- break;\r
-\r
+ case R_AARCH64_PREL64:\r
+ case R_AARCH64_PREL32:\r
+ case R_AARCH64_PREL16:\r
case R_AARCH64_ADR_PREL_PG_HI21:\r
- // TODO : AArch64 'small' memory model.\r
- Error (NULL, 0, 3000, "Invalid", "WriteRelocations64(): %s unsupported ELF EM_AARCH64 relocation R_AARCH64_ADR_PREL_PG_HI21.", mInImageName);\r
- break;\r
-\r
case R_AARCH64_ADD_ABS_LO12_NC:\r
- // TODO : AArch64 'small' memory model.\r
- Error (NULL, 0, 3000, "Invalid", "WriteRelocations64(): %s unsupported ELF EM_AARCH64 relocation R_AARCH64_ADD_ABS_LO12_NC.", mInImageName);\r
+ case R_AARCH64_LDST8_ABS_LO12_NC:\r
+ case R_AARCH64_LDST16_ABS_LO12_NC:\r
+ case R_AARCH64_LDST32_ABS_LO12_NC:\r
+ case R_AARCH64_LDST64_ABS_LO12_NC:\r
+ case R_AARCH64_LDST128_ABS_LO12_NC:\r
+ //\r
+ // No fixups are required for relative relocations, provided that\r
+ // the relative offsets between sections have been preserved in\r
+ // the ELF to PE/COFF conversion. We have already asserted that\r
+ // this is the case in WriteSections64 ().\r
+ //\r
break;\r
\r
case R_AARCH64_ABS64:\r
)\r
{\r
UINT32 Len;\r
- UINT32 DebugOffset;\r
EFI_IMAGE_OPTIONAL_HEADER_UNION *NtHdr;\r
EFI_IMAGE_DATA_DIRECTORY *DataDir;\r
EFI_IMAGE_DEBUG_DIRECTORY_ENTRY *Dir;\r
EFI_IMAGE_DEBUG_CODEVIEW_NB10_ENTRY *Nb10;\r
\r
Len = strlen(mInImageName) + 1;\r
- DebugOffset = mCoffOffset;\r
\r
- mCoffOffset += sizeof(EFI_IMAGE_DEBUG_DIRECTORY_ENTRY)\r
- + sizeof(EFI_IMAGE_DEBUG_CODEVIEW_NB10_ENTRY)\r
- + Len;\r
- mCoffOffset = CoffAlign(mCoffOffset);\r
-\r
- mCoffFile = realloc(mCoffFile, mCoffOffset);\r
- memset(mCoffFile + DebugOffset, 0, mCoffOffset - DebugOffset);\r
-\r
- Dir = (EFI_IMAGE_DEBUG_DIRECTORY_ENTRY*)(mCoffFile + DebugOffset);\r
+ Dir = (EFI_IMAGE_DEBUG_DIRECTORY_ENTRY*)(mCoffFile + mDebugOffset);\r
Dir->Type = EFI_IMAGE_DEBUG_TYPE_CODEVIEW;\r
Dir->SizeOfData = sizeof(EFI_IMAGE_DEBUG_CODEVIEW_NB10_ENTRY) + Len;\r
- Dir->RVA = DebugOffset + sizeof(EFI_IMAGE_DEBUG_DIRECTORY_ENTRY);\r
- Dir->FileOffset = DebugOffset + sizeof(EFI_IMAGE_DEBUG_DIRECTORY_ENTRY);\r
+ Dir->RVA = mDebugOffset + sizeof(EFI_IMAGE_DEBUG_DIRECTORY_ENTRY);\r
+ Dir->FileOffset = mDebugOffset + sizeof(EFI_IMAGE_DEBUG_DIRECTORY_ENTRY);\r
\r
Nb10 = (EFI_IMAGE_DEBUG_CODEVIEW_NB10_ENTRY*)(Dir + 1);\r
Nb10->Signature = CODEVIEW_SIGNATURE_NB10;\r
\r
NtHdr = (EFI_IMAGE_OPTIONAL_HEADER_UNION *)(mCoffFile + mNtHdrOffset);\r
DataDir = &NtHdr->Pe32Plus.OptionalHeader.DataDirectory[EFI_IMAGE_DIRECTORY_ENTRY_DEBUG];\r
- DataDir->VirtualAddress = DebugOffset;\r
- DataDir->Size = mCoffOffset - DebugOffset;\r
- if (DataDir->Size == 0) {\r
- // If no debug, null out the directory entry and don't add the .debug section\r
- DataDir->VirtualAddress = 0;\r
- NtHdr->Pe32Plus.FileHeader.NumberOfSections--;\r
- } else {\r
- DataDir->VirtualAddress = DebugOffset;\r
- CreateSectionHeader (".debug", DebugOffset, mCoffOffset - DebugOffset,\r
- EFI_IMAGE_SCN_CNT_INITIALIZED_DATA\r
- | EFI_IMAGE_SCN_MEM_DISCARDABLE\r
- | EFI_IMAGE_SCN_MEM_READ);\r
-\r
- }\r
+ DataDir->VirtualAddress = mDebugOffset;\r
+ DataDir->Size = Dir->SizeOfData + sizeof(EFI_IMAGE_DEBUG_DIRECTORY_ENTRY);\r
}\r
\r
STATIC\r