-/** @file \r
-x64 Long Mode Virtual Memory Management Definitions \r
+/** @file\r
+x64 Long Mode Virtual Memory Management Definitions\r
\r
References:\r
1) IA-32 Intel(R) Atchitecture Software Developer's Manual Volume 1:Basic Architecture, Intel\r
2) IA-32 Intel(R) Atchitecture Software Developer's Manual Volume 2:Instruction Set Reference, Intel\r
3) IA-32 Intel(R) Atchitecture Software Developer's Manual Volume 3:System Programmer's Guide, Intel\r
4) AMD64 Architecture Programmer's Manual Volume 2: System Programming\r
- \r
-Copyright (c) 2006 - 2014, Intel Corporation. All rights reserved.<BR>\r
-This program and the accompanying materials \r
-are licensed and made available under the terms and conditions of the BSD License \r
-which accompanies this distribution. The full text of the license may be found at \r
-http://opensource.org/licenses/bsd-license.php \r
- \r
-THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r
-WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r
- \r
+\r
+Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>\r
+This program and the accompanying materials\r
+are licensed and made available under the terms and conditions of the BSD License\r
+which accompanies this distribution. The full text of the license may be found at\r
+http://opensource.org/licenses/bsd-license.php\r
+\r
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
**/\r
\r
#ifndef _VIRTUAL_MEMORY_H_\r
UINT64 CacheDisabled:1; // 0 = Cached, 1=Non-Cached\r
UINT64 Accessed:1; // 0 = Not accessed, 1 = Accessed (set by CPU)\r
UINT64 Dirty:1; // 0 = Not Dirty, 1 = written by processor on access to page\r
- UINT64 PAT:1; // 0 = Ignore Page Attribute Table \r
+ UINT64 PAT:1; // 0 = Ignore Page Attribute Table\r
UINT64 Global:1; // 0 = Not global page, 1 = global page TLB not cleared on CR3 write\r
UINT64 Available:3; // Available for use by system software\r
UINT64 PageTableBaseAddress:40; // Page Table Base Address\r
UINT64 CacheDisabled:1; // 0 = Cached, 1=Non-Cached\r
UINT64 Accessed:1; // 0 = Not accessed, 1 = Accessed (set by CPU)\r
UINT64 Dirty:1; // 0 = Not Dirty, 1 = written by processor on access to page\r
- UINT64 MustBe1:1; // Must be 1 \r
+ UINT64 MustBe1:1; // Must be 1\r
UINT64 Global:1; // 0 = Not global page, 1 = global page TLB not cleared on CR3 write\r
UINT64 Available:3; // Available for use by system software\r
UINT64 PAT:1; //\r
\r
#pragma pack()\r
\r
-#endif \r
+#endif\r