orr r0, r0, #0x00000002 /* set bit 1 (A) Align */\r
orr r0, r0, #0x00001000 /* set bit 12 (I) enable I-Cache */\r
mcr p15, 0, r0, c1, c0, 0\r
+\r
+ // Enable NEON register in case folks want to use them for optimizations (CopyMem)\r
+ mrc p15, 0, r0, c1, c0, 2\r
+ orr r0, r0, #0x00f00000 // Enable VPF access (V* instructions)\r
+ mcr p15, 0, r0, c1, c0, 2\r
+ mov r0, #0x40000000 // Set EN bit in FPEXC\r
+ mcr p10,#0x7,r0,c8,c0,#0 // msr FPEXC,r0 in ARM assembly\r
+ \r
\r
// Set CPU vectors to start of DRAM\r
LoadConstantToReg (FixedPcdGet32(PcdCpuVectorBaseAddress) ,r0) // Get vector base\r