ArmVirtPkg/FdtParser: avoid unaligned accesses with the MMU off

[mirror_edk2.git] / BeagleBoardPkg / Sec / Cache.c

diff --git a/BeagleBoardPkg/Sec/Cache.c b/BeagleBoardPkg/Sec/Cache.c
old mode 100755 (executable)
new mode 100644 (file)
index facc5de..7399eef
--- a/BeagleBoardPkg/Sec/Cache.c
+++ b/BeagleBoardPkg/Sec/Cache.c
@@ -1,8 +1,8 @@
 /** @file\r
 \r
-  Copyright (c) 2008-2009, Apple Inc. All rights reserved.\r
-  \r
-  All rights reserved. This program and the accompanying materials\r
+  Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>\r
+\r
+  This program and the accompanying materials\r
   are licensed and made available under the terms and conditions of the BSD License\r
   which accompanies this distribution.  The full text of the license may be found at\r
   http://opensource.org/licenses/bsd-license.php\r
@@ -38,14 +38,11 @@ InitCache (
   IN  UINT32  MemoryLength\r
   )\r
 {\r
-  UINTN                         UncachedMemoryMask;\r
   UINT32                        CacheAttributes;\r
   ARM_MEMORY_REGION_DESCRIPTOR  MemoryTable[5];\r
   VOID                          *TranslationTableBase;\r
   UINTN                         TranslationTableSize;\r
 \r
-  UncachedMemoryMask = PcdGet64(PcdArmUncachedMemoryMask);\r
-\r
   if (FeaturePcdGet(PcdCacheEnable) == TRUE) {\r
     CacheAttributes = DDR_ATTRIBUTES_CACHED;\r
   } else {\r
@@ -58,31 +55,25 @@ InitCache (
   MemoryTable[0].Length       = MemoryLength;\r
   MemoryTable[0].Attributes   = (ARM_MEMORY_REGION_ATTRIBUTES)CacheAttributes;\r
 \r
-  // Uncached DDR Mirror\r
-  MemoryTable[1].PhysicalBase = MemoryBase;\r
-  MemoryTable[1].VirtualBase  = MemoryBase | UncachedMemoryMask;\r
-  MemoryTable[1].Length       = MemoryLength;\r
-  MemoryTable[1].Attributes   = DDR_ATTRIBUTES_UNCACHED;\r
-\r
   // SOC Registers. L3 interconnects\r
-  MemoryTable[2].PhysicalBase = SOC_REGISTERS_L3_PHYSICAL_BASE;\r
-  MemoryTable[2].VirtualBase  = SOC_REGISTERS_L3_PHYSICAL_BASE;\r
-  MemoryTable[2].Length       = SOC_REGISTERS_L3_PHYSICAL_LENGTH;\r
-  MemoryTable[2].Attributes   = SOC_REGISTERS_L3_ATTRIBUTES;\r
-  \r
+  MemoryTable[1].PhysicalBase = SOC_REGISTERS_L3_PHYSICAL_BASE;\r
+  MemoryTable[1].VirtualBase  = SOC_REGISTERS_L3_PHYSICAL_BASE;\r
+  MemoryTable[1].Length       = SOC_REGISTERS_L3_PHYSICAL_LENGTH;\r
+  MemoryTable[1].Attributes   = SOC_REGISTERS_L3_ATTRIBUTES;\r
+\r
   // SOC Registers. L4 interconnects\r
-  MemoryTable[3].PhysicalBase = SOC_REGISTERS_L4_PHYSICAL_BASE;\r
-  MemoryTable[3].VirtualBase  = SOC_REGISTERS_L4_PHYSICAL_BASE;\r
-  MemoryTable[3].Length       = SOC_REGISTERS_L4_PHYSICAL_LENGTH;\r
-  MemoryTable[3].Attributes   = SOC_REGISTERS_L4_ATTRIBUTES;\r
+  MemoryTable[2].PhysicalBase = SOC_REGISTERS_L4_PHYSICAL_BASE;\r
+  MemoryTable[2].VirtualBase  = SOC_REGISTERS_L4_PHYSICAL_BASE;\r
+  MemoryTable[2].Length       = SOC_REGISTERS_L4_PHYSICAL_LENGTH;\r
+  MemoryTable[2].Attributes   = SOC_REGISTERS_L4_ATTRIBUTES;\r
 \r
   // End of Table\r
-  MemoryTable[4].PhysicalBase = 0;\r
-  MemoryTable[4].VirtualBase  = 0;\r
-  MemoryTable[4].Length       = 0;\r
-  MemoryTable[4].Attributes   = (ARM_MEMORY_REGION_ATTRIBUTES)0;\r
-  \r
+  MemoryTable[3].PhysicalBase = 0;\r
+  MemoryTable[3].VirtualBase  = 0;\r
+  MemoryTable[3].Length       = 0;\r
+  MemoryTable[3].Attributes   = (ARM_MEMORY_REGION_ATTRIBUTES)0;\r
+\r
   ArmConfigureMmu (MemoryTable, &TranslationTableBase, &TranslationTableSize);\r
-  \r
+\r
   BuildMemoryAllocationHob((EFI_PHYSICAL_ADDRESS)(UINTN)TranslationTableBase, TranslationTableSize, EfiBootServicesData);\r
 }\r