UefiCpuPkg/PiSmmCpu: Always set WP in CR0

[mirror_edk2.git] / BeagleBoardPkg / Sec / Sec.c

diff --git a/BeagleBoardPkg/Sec/Sec.c b/BeagleBoardPkg/Sec/Sec.c
index 50db72ae698e99ce2cffb07dfd6004ccd655a33e..0708396d9792514efa981e3e14f6855424025fcc 100644 (file)
--- a/BeagleBoardPkg/Sec/Sec.c
+++ b/BeagleBoardPkg/Sec/Sec.c
@@ -2,7 +2,7 @@
   C Entry point for the SEC. First C code after the reset vector.\r
 \r
   Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>\r
-  \r
+\r
   This program and the accompanying materials\r
   are licensed and made available under the terms and conditions of the BSD License\r
   which accompanies this distribution.  The full text of the license may be found at\r
@@ -93,9 +93,9 @@ UartInit (
   MmioWrite32 (UartBaseAddress + UART_MCR_REG, UART_MCR_RTS_FORCE_ACTIVE | UART_MCR_DTR_FORCE_ACTIVE);\r
 \r
   // Clear & enable fifos\r
-  MmioWrite32 (UartBaseAddress + UART_FCR_REG, UART_FCR_TX_FIFO_CLEAR | UART_FCR_RX_FIFO_CLEAR | UART_FCR_FIFO_ENABLE);  \r
+  MmioWrite32 (UartBaseAddress + UART_FCR_REG, UART_FCR_TX_FIFO_CLEAR | UART_FCR_RX_FIFO_CLEAR | UART_FCR_FIFO_ENABLE);\r
 \r
-  // Restore MODE_SELECT \r
+  // Restore MODE_SELECT\r
   MmioWrite32 (UartBaseAddress + UART_MDR1_REG, UART_MDR1_MODE_SELECT_UART_16X);\r
 }\r
 \r
@@ -153,8 +153,8 @@ CEntryPoint (
 \r
   // Start talking\r
   UartInit ();\r
- \r
-  InitializeDebugAgent (DEBUG_AGENT_INIT_PREMEM_SEC, NULL);\r
+\r
+  InitializeDebugAgent (DEBUG_AGENT_INIT_PREMEM_SEC, NULL, NULL);\r
   SaveAndSetDebugTimerInterrupt (TRUE);\r
 \r
   DEBUG ((EFI_D_ERROR, "UART Enabled\n"));\r
@@ -179,7 +179,7 @@ CEntryPoint (
 \r
   // Load the DXE Core and transfer control to it\r
   LoadDxeCoreFromFv (NULL, 0);\r
-  \r
+\r
   // DXE Core should always load and never return\r
   ASSERT (FALSE);\r
 }\r