Clean ECP for build failure.

[mirror_edk2.git] / DuetPkg / PciRootBridgeNoEnumerationDxe / Ia32 / PcatIo.c

diff --git a/DuetPkg/PciRootBridgeNoEnumerationDxe/Ia32/PcatIo.c b/DuetPkg/PciRootBridgeNoEnumerationDxe/Ia32/PcatIo.c
index d697390fa9531b3fd39874a19abbf264057c40fa..9edbc698bc76833f4a130e82d9abb04b761c5125 100644 (file)
--- a/DuetPkg/PciRootBridgeNoEnumerationDxe/Ia32/PcatIo.c
+++ b/DuetPkg/PciRootBridgeNoEnumerationDxe/Ia32/PcatIo.c
@@ -1,6 +1,6 @@
 /*++\r
 \r
-Copyright (c) 2005 - 2006, Intel Corporation                                                         \r
+Copyright (c) 2005 - 2008, Intel Corporation                                                         \r
 All rights reserved. This program and the accompanying materials                          \r
 are licensed and made available under the terms and conditions of the BSD License         \r
 which accompanies this distribution.  The full text of the license may be found at        \r
@@ -22,8 +22,8 @@ Revision History
 \r
 #include "PcatPciRootBridge.h"\r
 \r
-static BOOLEAN                  mPciOptionRomTableInstalled = FALSE;\r
-static EFI_PCI_OPTION_ROM_TABLE mPciOptionRomTable          = {0, NULL};\r
+BOOLEAN                  mPciOptionRomTableInstalled = FALSE;\r
+EFI_PCI_OPTION_ROM_TABLE mPciOptionRomTable          = {0, NULL};\r
 \r
 EFI_STATUS\r
 EFIAPI\r
@@ -210,7 +210,6 @@ PcatRootBridgeIoPciRW (
   return EFI_SUCCESS;\r
 }\r
 \r
-static\r
 VOID\r
 ScanPciBus(\r
   EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL  *IoDev,\r
@@ -299,7 +298,6 @@ ScanPciBus(
   }\r
 }\r
 \r
-static\r
 VOID\r
 CheckForRom (\r
   EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL  *IoDev,\r
@@ -525,7 +523,6 @@ CheckForRom (
   IoDev->Pci.Write (IoDev, EfiPciWidthUint32, Address, sizeof(PciHeader)/sizeof(UINT32), &PciHeader);\r
 }\r
 \r
-static\r
 VOID\r
 SaveCommandRegister (\r
   EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL  *IoDev,\r
@@ -563,7 +560,6 @@ SaveCommandRegister (
   IoDev->Pci.Write (IoDev, EfiPciWidthUint16, Address, 1, &Command);\r
 }\r
 \r
-static\r
 VOID\r
 RestoreCommandRegister (\r
   EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL  *IoDev,\r
@@ -612,7 +608,7 @@ ScanPciRootBridgeForRoms(
     mPciOptionRomTableInstalled = TRUE;\r
   }\r
 \r
-  Status = IoDev->Configuration(IoDev, &Descriptors);\r
+  Status = IoDev->Configuration(IoDev, (VOID **)&Descriptors);\r
   if (EFI_ERROR (Status) || Descriptors == NULL) {\r
     return EFI_NOT_FOUND;\r
   }\r
@@ -636,7 +632,7 @@ ScanPciRootBridgeForRoms(
       //\r
       // Find Memory Descriptors that are less than 4GB, so the PPB Memory Window can be used for downstream devices\r
       //\r
-      if (Descriptors->AddrRangeMax < 0x100000000) {\r
+      if (Descriptors->AddrRangeMax < 0x100000000ULL) {\r
         //\r
         // Find the largest Non-Prefetchable Memory Descriptor that is less than 4GB\r
         //\r
@@ -683,7 +679,7 @@ ScanPciRootBridgeForRoms(
   Status = gBS->AllocatePool(\r
                   EfiBootServicesData,\r
                   sizeof(UINT16) * (MaxBus - MinBus + 1) * (PCI_MAX_DEVICE+1) * (PCI_MAX_FUNC+1),\r
-                  &Context.CommandRegisterBuffer\r
+                  (VOID **)&Context.CommandRegisterBuffer\r
                   );\r
 \r
   if (EFI_ERROR (Status)) {\r