MdeModulePkg/PciSioSerial: Fix bad EOL

[mirror_edk2.git] / DuetPkg / PciRootBridgeNoEnumerationDxe / Ia32 / PcatIo.c

diff --git a/DuetPkg/PciRootBridgeNoEnumerationDxe/Ia32/PcatIo.c b/DuetPkg/PciRootBridgeNoEnumerationDxe/Ia32/PcatIo.c
index dc4530aa6837b37f98fb12eb0908408687fc5da5..d479e7f9fcce85c5f5b49a75a3cb17fa687fa89e 100644 (file)
--- a/DuetPkg/PciRootBridgeNoEnumerationDxe/Ia32/PcatIo.c
+++ b/DuetPkg/PciRootBridgeNoEnumerationDxe/Ia32/PcatIo.c
@@ -1,7 +1,7 @@
 /*++\r
 \r
-Copyright (c) 2005 - 2008, Intel Corporation                                                         \r
-All rights reserved. This program and the accompanying materials                          \r
+Copyright (c) 2005 - 2012, Intel Corporation. All rights reserved.<BR>\r
+This program and the accompanying materials                          \r
 are licensed and made available under the terms and conditions of the BSD License         \r
 which accompanies this distribution.  The full text of the license may be found at        \r
 http://opensource.org/licenses/bsd-license.php                                            \r
@@ -102,7 +102,7 @@ PcatRootBridgeIoPciRW (
   UINT64                            PciExpressRegAddr;\r
   BOOLEAN                           UsePciExpressAccess;\r
 \r
-  if (Width < 0 || Width >= EfiPciWidthMaximum) {\r
+  if ((UINT32)Width >= EfiPciWidthMaximum) {\r
     return EFI_INVALID_PARAMETER;\r
   }\r
   \r
@@ -114,11 +114,11 @@ PcatRootBridgeIoPciRW (
 \r
   InStride    = 1 << (Width & 0x03);\r
   OutStride   = InStride;\r
-  if (Width >= EfiCpuIoWidthFifoUint8 && Width <= EfiCpuIoWidthFifoUint64) {\r
+  if (Width >= EfiPciWidthFifoUint8 && Width <= EfiPciWidthFifoUint64) {\r
     InStride = 0;\r
   }\r
 \r
-  if (Width >= EfiCpuIoWidthFillUint8 && Width <= EfiCpuIoWidthFillUint64) {\r
+  if (Width >= EfiPciWidthFillUint8 && Width <= EfiPciWidthFillUint64) {\r
     OutStride = 0;\r
   }\r
 \r
@@ -131,7 +131,7 @@ PcatRootBridgeIoPciRW (
     // Check PciExpressBaseAddress\r
     //\r
     if ((PrivateData->PciExpressBaseAddress == 0) ||\r
-        (PrivateData->PciExpressBaseAddress >= EFI_MAX_ADDRESS)) {\r
+        (PrivateData->PciExpressBaseAddress >= MAX_ADDRESS)) {\r
       return EFI_UNSUPPORTED;\r
     } else {\r
       UsePciExpressAccess = TRUE;\r
@@ -436,8 +436,10 @@ CheckForRom (
 \r
           Pcir.ImageLength = 0;\r
 \r
-          if (EfiRomHeader.Signature == 0xaa55) {\r
-\r
+          if (EfiRomHeader.Signature == PCI_EXPANSION_ROM_HEADER_SIGNATURE &&\r
+              EfiRomHeader.PcirOffset != 0 &&\r
+              (EfiRomHeader.PcirOffset & 3) == 0 &&\r
+              RomBarSize + EfiRomHeader.PcirOffset + sizeof (PCI_DATA_STRUCTURE) <= MaxRomSize) {\r
             ZeroMem (&Pcir, sizeof(Pcir));\r
             IoDev->Mem.Read (\r
               IoDev, \r
@@ -447,6 +449,12 @@ CheckForRom (
               &Pcir\r
               );\r
 \r
+            if (Pcir.Signature != PCI_DATA_STRUCTURE_SIGNATURE) {\r
+              break;\r
+            }\r
+            if (RomBarSize + Pcir.ImageLength * 512 > MaxRomSize) {\r
+              break;\r
+            }\r
             if ((Pcir.Indicator & 0x80) == 0x00) {\r
               LastImage = FALSE;\r
             }\r