]> git.proxmox.com Git - mirror_edk2.git/blobdiff - DuetPkg/PciRootBridgeNoEnumerationDxe/PcatPciRootBridge.c
Per EdkII IntelFrameworkPkg code review instructions, add comments before each gui...
[mirror_edk2.git] / DuetPkg / PciRootBridgeNoEnumerationDxe / PcatPciRootBridge.c
index ff53bb5c78bf1c63f1b06863374442f7d6dd5c36..d1280245942f584801716dc1f9a074af1b038ef0 100644 (file)
@@ -1,6 +1,6 @@
 /*++\r
 \r
-Copyright (c) 2005 - 2006, Intel Corporation                                                         \r
+Copyright (c) 2005 - 2008, Intel Corporation                                                         \r
 All rights reserved. This program and the accompanying materials                          \r
 are licensed and made available under the terms and conditions of the BSD License         \r
 which accompanies this distribution.  The full text of the license may be found at        \r
@@ -62,7 +62,7 @@ Returns:
   //\r
   // Initialize gCpuIo now since the chipset init code requires it.\r
   //\r
-  Status = gBS->LocateProtocol (&gEfiCpuIoProtocolGuid, NULL, &gCpuIo);\r
+  Status = gBS->LocateProtocol (&gEfiCpuIoProtocolGuid, NULL, (VOID **)&gCpuIo);\r
   ASSERT_EFI_ERROR (Status);\r
 \r
   //\r
@@ -79,7 +79,7 @@ Returns:
     Status = gBS->AllocatePool(\r
                     EfiBootServicesData,\r
                     sizeof (PCAT_PCI_ROOT_BRIDGE_INSTANCE),\r
-                    &PrivateData\r
+                    (VOID **)&PrivateData\r
                     );\r
     if (EFI_ERROR (Status)) {\r
       goto Done;\r
@@ -104,10 +104,10 @@ Returns:
 \r
     PrivateData->IoBase      = 0xffffffff;\r
     PrivateData->MemBase     = 0xffffffff;\r
-    PrivateData->Mem32Base   = 0xffffffffffffffff;\r
-    PrivateData->Pmem32Base  = 0xffffffffffffffff;\r
-    PrivateData->Mem64Base   = 0xffffffffffffffff;\r
-    PrivateData->Pmem64Base  = 0xffffffffffffffff;\r
+    PrivateData->Mem32Base   = 0xffffffffffffffffULL;\r
+    PrivateData->Pmem32Base  = 0xffffffffffffffffULL;\r
+    PrivateData->Mem64Base   = 0xffffffffffffffffULL;\r
+    PrivateData->Pmem64Base  = 0xffffffffffffffffULL;\r
 \r
     //\r
     // The default mechanism for performing PCI Configuration cycles is to \r
@@ -151,7 +151,7 @@ Returns:
     //\r
     // Build the EFI Device Path Protocol instance for this PCI Root Bridge\r
     //\r
-    Status = PcatRootBridgeDevicePathConstructor (&PrivateData->DevicePath, PciRootBridgeIndex, (PrivateData->PciExpressBaseAddress != 0) ? TRUE : FALSE);\r
+    Status = PcatRootBridgeDevicePathConstructor (&PrivateData->DevicePath, PciRootBridgeIndex, (BOOLEAN)((PrivateData->PciExpressBaseAddress != 0) ? TRUE : FALSE));\r
     if (EFI_ERROR (Status)) {\r
       goto Done;\r
     }\r
@@ -183,7 +183,7 @@ Returns:
                                        &PrivateData->Io, \r
                                        EfiPciWidthUint16, \r
                                        Address, \r
-                                       sizeof (VendorId), \r
+                                       sizeof (VendorId) / sizeof (UINT16)\r
                                        &VendorId\r
                                        );\r
         if ((EFI_ERROR (Status)) || ((VendorId == 0xffff) && (Function == 0))) {\r
@@ -205,9 +205,9 @@ Returns:
         //\r
         Status = PrivateData->Io.Pci.Read (\r
                                        &PrivateData->Io, \r
-                                       EfiPciWidthUint32\r
+                                       EfiPciWidthUint16\r
                                        Address, \r
-                                       sizeof (PciConfigurationHeader) / sizeof (UINT32), \r
+                                       sizeof (PciConfigurationHeader) / sizeof (UINT16), \r
                                        &PciConfigurationHeader\r
                                        );\r
         if (EFI_ERROR (Status)) {\r
@@ -217,6 +217,7 @@ Returns:
           break;\r
         }\r
 \r
+\r
         //\r
         // Increment the number of PCI device found on the primary bus of the PCI root bridge\r
         //\r
@@ -592,7 +593,7 @@ Returns:
     Status = gBS->AllocatePool (\r
                     EfiBootServicesData, \r
                     sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR) + sizeof (EFI_ACPI_END_TAG_DESCRIPTOR),\r
-                    &PrivateData->Configuration\r
+                    (VOID **)&PrivateData->Configuration\r
                     );\r
     if (EFI_ERROR (Status )) {\r
       return Status;\r
@@ -621,7 +622,7 @@ Returns:
   Status = gBS->AllocatePool (\r
                   EfiBootServicesData, \r
                   sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR) * NumConfig + sizeof (EFI_ACPI_END_TAG_DESCRIPTOR),\r
-                  &PrivateData->Configuration\r
+                  (VOID **)&PrivateData->Configuration\r
                   );\r
   if (EFI_ERROR (Status )) {\r
     return Status;\r
@@ -803,7 +804,7 @@ Returns:
   if ( *Value == 0 ) {\r
     return EFI_DEVICE_ERROR;\r
   }\r
-  return EFI_SUCCESS;\r
+  return Status;\r
 }\r
 \r
 EFI_STATUS\r
@@ -974,24 +975,14 @@ Returns:
   UINTN                                    BufferSize;\r
   UINT32                                   Index;\r
   UINT32                                   Number;\r
-  VOID                                     *HobList;\r
-  EFI_STATUS                               Status;\r
   EFI_PEI_HOB_POINTERS                     GuidHob;\r
 \r
-  //\r
-  // Get Hob List from configuration table\r
-  //\r
-  Status = EfiGetSystemConfigurationTable (&gEfiHobListGuid, &HobList);\r
-  if (EFI_ERROR (Status)) {\r
-    return 0;\r
-  }\r
-\r
   //\r
   // Get PciExpressAddressInfo Hob\r
   //\r
   PciExpressBaseAddressInfo = NULL;\r
   BufferSize                = 0;\r
-  GuidHob.Raw = GetNextGuidHob (&gEfiPciExpressBaseAddressGuid, &HobList);\r
+  GuidHob.Raw = GetFirstGuidHob (&gEfiPciExpressBaseAddressGuid);\r
   if (GuidHob.Raw != NULL) {\r
     PciExpressBaseAddressInfo = GET_GUID_HOB_DATA (GuidHob.Guid);\r
     BufferSize                = GET_GUID_HOB_DATA_SIZE (GuidHob.Guid);\r