ShellBinPkg: Arm/AArch64 Shell binary update.

[mirror_edk2.git] / DuetPkg / PciRootBridgeNoEnumerationDxe / PcatPciRootBridge.h

diff --git a/DuetPkg/PciRootBridgeNoEnumerationDxe/PcatPciRootBridge.h b/DuetPkg/PciRootBridgeNoEnumerationDxe/PcatPciRootBridge.h
index 960ad9a27fb823c5fec22caae549f6e0e5c1d609..0450fcf672764a4e695fd96bae5fab0c421f925e 100644 (file)
--- a/DuetPkg/PciRootBridgeNoEnumerationDxe/PcatPciRootBridge.h
+++ b/DuetPkg/PciRootBridgeNoEnumerationDxe/PcatPciRootBridge.h
@@ -1,7 +1,7 @@
 /*++\r
 \r
-Copyright (c) 2005 - 2006, Intel Corporation                                                         \r
-All rights reserved. This program and the accompanying materials                          \r
+Copyright (c) 2005 - 2006, Intel Corporation. All rights reserved.<BR>\r
+This program and the accompanying materials                          \r
 are licensed and made available under the terms and conditions of the BSD License         \r
 which accompanies this distribution.  The full text of the license may be found at        \r
 http://opensource.org/licenses/bsd-license.php                                            \r
@@ -24,7 +24,7 @@ Abstract:
 #include <PiDxe.h>\r
 #include <Protocol/PciRootBridgeIo.h>\r
 #include <Protocol/DeviceIo.h>\r
-#include <Protocol/CpuIo.h>\r
+#include <Protocol/CpuIo2.h>\r
 \r
 #include <Library/UefiLib.h>\r
 #include <Library/BaseLib.h>\r
@@ -41,10 +41,12 @@ Abstract:
 \r
 #include <IndustryStandard/Acpi.h>\r
 #include <IndustryStandard/Pci.h>\r
+\r
+#define PCI_MAX_SEGMENT   0\r
 //\r
 // Driver Instance Data Prototypes\r
 //\r
-#define PCAT_PCI_ROOT_BRIDGE_SIGNATURE  EFI_SIGNATURE_32('p', 'c', 'r', 'b')\r
+#define PCAT_PCI_ROOT_BRIDGE_SIGNATURE  SIGNATURE_32('p', 'c', 'r', 'b')\r
 \r
 typedef struct {\r
   UINT32                            Signature;\r
@@ -52,7 +54,7 @@ typedef struct {
                                     \r
   EFI_DEVICE_PATH_PROTOCOL          *DevicePath;\r
   EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL   Io;\r
-  EFI_CPU_IO_PROTOCOL               *CpuIo;\r
+  EFI_CPU_IO2_PROTOCOL              *CpuIo;\r
 \r
   UINT32                            RootBridgeNumber;\r
   UINT32                            PrimaryBus;\r
@@ -207,6 +209,26 @@ GetPciExpressBaseAddressForRootBridge (
   IN UINTN    RootBridgeNumber\r
   );\r
 \r
+EFI_STATUS\r
+EFIAPI\r
+PcatRootBridgeIoIoRead (\r
+  IN     EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL        *This,\r
+  IN     EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH  Width,\r
+  IN     UINT64                                 UserAddress,\r
+  IN     UINTN                                  Count,\r
+  IN OUT VOID                                   *UserBuffer\r
+  );\r
+\r
+EFI_STATUS\r
+EFIAPI\r
+PcatRootBridgeIoIoWrite (\r
+  IN     EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL        *This,\r
+  IN     EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH  Width,\r
+  IN     UINT64                                 UserAddress,\r
+  IN     UINTN                                  Count,\r
+  IN OUT VOID                                   *UserBuffer\r
+  );\r
+\r
 //\r
 // Driver entry point prototype\r
 //\r
@@ -217,6 +239,6 @@ InitializePcatPciRootBridge (
   IN EFI_SYSTEM_TABLE *SystemTable\r
   );\r
 \r
-extern EFI_CPU_IO_PROTOCOL  *gCpuIo;\r
+extern EFI_CPU_IO2_PROTOCOL  *gCpuIo;\r
 \r
 #endif\r