EArmObjSmmuInterruptArray, ///< 26 - SMMU Interrupt Array\r
EArmObjProcHierarchyInfo, ///< 27 - Processor Hierarchy Info\r
EArmObjCacheInfo, ///< 28 - Cache Info\r
- EArmObjProcNodeIdInfo, ///< 29 - Processor Node ID Info\r
+ EArmObjReserved29, ///< 29 - Reserved\r
EArmObjCmRef, ///< 30 - CM Object Reference\r
EArmObjMemoryAffinityInfo, ///< 31 - Memory Affinity Info\r
EArmObjDeviceHandleAcpi, ///< 32 - Device Handle Acpi\r
EArmObjGenericInitiatorAffinityInfo, ///< 34 - Generic Initiator Affinity\r
EArmObjSerialPortInfo, ///< 35 - Generic Serial Port Info\r
EArmObjCmn600Info, ///< 36 - CMN-600 Info\r
+ EArmObjLpiInfo, ///< 37 - Lpi Info\r
EArmObjMax\r
} EARM_OBJECT_ID;\r
\r
/** This is the ARM_BOOT_ARCH flags field of the FADT Table\r
described in the ACPI Table Specification.\r
*/\r
- UINT16 BootArchFlags;\r
+ UINT16 BootArchFlags;\r
} CM_ARM_BOOT_ARCH_INFO;\r
\r
/** A structure that describes the\r
/** This is the Preferred_PM_Profile field of the FADT Table\r
described in the ACPI Specification\r
*/\r
- UINT8 PowerManagementProfile;\r
+ UINT8 PowerManagementProfile;\r
} CM_ARM_POWER_MANAGEMENT_PROFILE_INFO;\r
\r
/** A structure that describes the\r
*/\r
typedef struct CmArmGicCInfo {\r
/// The GIC CPU Interface number.\r
- UINT32 CPUInterfaceNumber;\r
+ UINT32 CPUInterfaceNumber;\r
\r
/** The ACPI Processor UID. This must match the\r
_UID of the CPU Device object information described\r
in the DSDT/SSDT for the CPU.\r
*/\r
- UINT32 AcpiProcessorUid;\r
+ UINT32 AcpiProcessorUid;\r
\r
/** The flags field as described by the GICC structure\r
in the ACPI Specification.\r
*/\r
- UINT32 Flags;\r
+ UINT32 Flags;\r
\r
/** The parking protocol version field as described by\r
the GICC structure in the ACPI Specification.\r
*/\r
- UINT32 ParkingProtocolVersion;\r
+ UINT32 ParkingProtocolVersion;\r
\r
/** The Performance Interrupt field as described by\r
the GICC structure in the ACPI Specification.\r
*/\r
- UINT32 PerformanceInterruptGsiv;\r
+ UINT32 PerformanceInterruptGsiv;\r
\r
/** The CPU Parked address field as described by\r
the GICC structure in the ACPI Specification.\r
*/\r
- UINT64 ParkedAddress;\r
+ UINT64 ParkedAddress;\r
\r
/** The base address for the GIC CPU Interface\r
as described by the GICC structure in the\r
ACPI Specification.\r
*/\r
- UINT64 PhysicalBaseAddress;\r
+ UINT64 PhysicalBaseAddress;\r
\r
/** The base address for GICV interface\r
as described by the GICC structure in the\r
ACPI Specification.\r
*/\r
- UINT64 GICV;\r
+ UINT64 GICV;\r
\r
/** The base address for GICH interface\r
as described by the GICC structure in the\r
ACPI Specification.\r
*/\r
- UINT64 GICH;\r
+ UINT64 GICH;\r
\r
/** The GICV maintenance interrupt\r
as described by the GICC structure in the\r
ACPI Specification.\r
*/\r
- UINT32 VGICMaintenanceInterrupt;\r
+ UINT32 VGICMaintenanceInterrupt;\r
\r
/** The base address for GICR interface\r
as described by the GICC structure in the\r
ACPI Specification.\r
*/\r
- UINT64 GICRBaseAddress;\r
+ UINT64 GICRBaseAddress;\r
\r
/** The MPIDR for the CPU\r
as described by the GICC structure in the\r
ACPI Specification.\r
*/\r
- UINT64 MPIDR;\r
+ UINT64 MPIDR;\r
\r
/** The Processor Power Efficiency class\r
as described by the GICC structure in the\r
ACPI Specification.\r
*/\r
- UINT8 ProcessorPowerEfficiencyClass;\r
+ UINT8 ProcessorPowerEfficiencyClass;\r
\r
/** Statistical Profiling Extension buffer overflow GSIV. Zero if\r
unsupported by this processor. This field was introduced in\r
ACPI 6.3 (MADT revision 5) and is therefore ignored when\r
generating MADT revision 4 or lower.\r
*/\r
- UINT16 SpeOverflowInterrupt;\r
+ UINT16 SpeOverflowInterrupt;\r
\r
/** The proximity domain to which the logical processor belongs.\r
This field is used to populate the GICC affinity structure\r
in the SRAT table.\r
*/\r
- UINT32 ProximityDomain;\r
+ UINT32 ProximityDomain;\r
\r
/** The clock domain to which the logical processor belongs.\r
This field is used to populate the GICC affinity structure\r
in the SRAT table.\r
*/\r
- UINT32 ClockDomain;\r
+ UINT32 ClockDomain;\r
\r
/** The GICC Affinity flags field as described by the GICC Affinity structure\r
in the SRAT table.\r
*/\r
- UINT32 AffinityFlags;\r
+ UINT32 AffinityFlags;\r
} CM_ARM_GICC_INFO;\r
\r
/** A structure that describes the\r
*/\r
typedef struct CmArmGicDInfo {\r
/// The Physical Base address for the GIC Distributor.\r
- UINT64 PhysicalBaseAddress;\r
+ UINT64 PhysicalBaseAddress;\r
\r
/** The global system interrupt\r
number where this GIC Distributor's\r
interrupt inputs start.\r
*/\r
- UINT32 SystemVectorBase;\r
+ UINT32 SystemVectorBase;\r
\r
/** The GIC version as described\r
by the GICD structure in the\r
ACPI Specification.\r
*/\r
- UINT8 GicVersion;\r
+ UINT8 GicVersion;\r
} CM_ARM_GICD_INFO;\r
\r
/** A structure that describes the\r
*/\r
typedef struct CmArmGicMsiFrameInfo {\r
/// The GIC MSI Frame ID\r
- UINT32 GicMsiFrameId;\r
+ UINT32 GicMsiFrameId;\r
\r
/// The Physical base address for the MSI Frame\r
- UINT64 PhysicalBaseAddress;\r
+ UINT64 PhysicalBaseAddress;\r
\r
/** The GIC MSI Frame flags\r
as described by the GIC MSI frame\r
structure in the ACPI Specification.\r
*/\r
- UINT32 Flags;\r
+ UINT32 Flags;\r
\r
/// SPI Count used by this frame\r
- UINT16 SPICount;\r
+ UINT16 SPICount;\r
\r
/// SPI Base used by this frame\r
- UINT16 SPIBase;\r
+ UINT16 SPIBase;\r
} CM_ARM_GIC_MSI_FRAME_INFO;\r
\r
/** A structure that describes the\r
/** The physical address of a page range\r
containing all GIC Redistributors.\r
*/\r
- UINT64 DiscoveryRangeBaseAddress;\r
+ UINT64 DiscoveryRangeBaseAddress;\r
\r
/// Length of the GIC Redistributor Discovery page range\r
- UINT32 DiscoveryRangeLength;\r
+ UINT32 DiscoveryRangeLength;\r
} CM_ARM_GIC_REDIST_INFO;\r
\r
/** A structure that describes the\r
*/\r
typedef struct CmArmGicItsInfo {\r
/// The GIC ITS ID\r
- UINT32 GicItsId;\r
+ UINT32 GicItsId;\r
\r
/// The physical address for the Interrupt Translation Service\r
- UINT64 PhysicalBaseAddress;\r
+ UINT64 PhysicalBaseAddress;\r
\r
/** The proximity domain to which the logical processor belongs.\r
This field is used to populate the GIC ITS affinity structure\r
in the SRAT table.\r
*/\r
- UINT32 ProximityDomain;\r
+ UINT32 ProximityDomain;\r
} CM_ARM_GIC_ITS_INFO;\r
\r
/** A structure that describes the\r
*/\r
typedef struct CmArmSerialPortInfo {\r
/// The physical base address for the serial port\r
- UINT64 BaseAddress;\r
+ UINT64 BaseAddress;\r
\r
/// The serial port interrupt\r
- UINT32 Interrupt;\r
+ UINT32 Interrupt;\r
\r
/// The serial port baud rate\r
- UINT64 BaudRate;\r
+ UINT64 BaudRate;\r
\r
/// The serial port clock\r
- UINT32 Clock;\r
+ UINT32 Clock;\r
\r
/// Serial Port subtype\r
- UINT16 PortSubtype;\r
+ UINT16 PortSubtype;\r
\r
/// The Base address length\r
- UINT64 BaseAddressLength;\r
+ UINT64 BaseAddressLength;\r
+\r
+ /// The access size\r
+ UINT8 AccessSize;\r
} CM_ARM_SERIAL_PORT_INFO;\r
\r
/** A structure that describes the\r
*/\r
typedef struct CmArmGenericTimerInfo {\r
/// The physical base address for the counter control frame\r
- UINT64 CounterControlBaseAddress;\r
+ UINT64 CounterControlBaseAddress;\r
\r
/// The physical base address for the counter read frame\r
- UINT64 CounterReadBaseAddress;\r
+ UINT64 CounterReadBaseAddress;\r
\r
/// The secure PL1 timer interrupt\r
- UINT32 SecurePL1TimerGSIV;\r
+ UINT32 SecurePL1TimerGSIV;\r
\r
/// The secure PL1 timer flags\r
- UINT32 SecurePL1TimerFlags;\r
+ UINT32 SecurePL1TimerFlags;\r
\r
/// The non-secure PL1 timer interrupt\r
- UINT32 NonSecurePL1TimerGSIV;\r
+ UINT32 NonSecurePL1TimerGSIV;\r
\r
/// The non-secure PL1 timer flags\r
- UINT32 NonSecurePL1TimerFlags;\r
+ UINT32 NonSecurePL1TimerFlags;\r
\r
/// The virtual timer interrupt\r
- UINT32 VirtualTimerGSIV;\r
+ UINT32 VirtualTimerGSIV;\r
\r
/// The virtual timer flags\r
- UINT32 VirtualTimerFlags;\r
+ UINT32 VirtualTimerFlags;\r
\r
/// The non-secure PL2 timer interrupt\r
- UINT32 NonSecurePL2TimerGSIV;\r
+ UINT32 NonSecurePL2TimerGSIV;\r
\r
/// The non-secure PL2 timer flags\r
- UINT32 NonSecurePL2TimerFlags;\r
+ UINT32 NonSecurePL2TimerFlags;\r
\r
/// GSIV for the virtual EL2 timer\r
- UINT32 VirtualPL2TimerGSIV;\r
+ UINT32 VirtualPL2TimerGSIV;\r
\r
/// Flags for the virtual EL2 timer\r
- UINT32 VirtualPL2TimerFlags;\r
+ UINT32 VirtualPL2TimerFlags;\r
} CM_ARM_GENERIC_TIMER_INFO;\r
\r
/** A structure that describes the\r
*/\r
typedef struct CmArmGTBlockTimerFrameInfo {\r
/// The Generic Timer frame number\r
- UINT8 FrameNumber;\r
+ UINT8 FrameNumber;\r
\r
/// The physical base address for the CntBase block\r
- UINT64 PhysicalAddressCntBase;\r
+ UINT64 PhysicalAddressCntBase;\r
\r
/// The physical base address for the CntEL0Base block\r
- UINT64 PhysicalAddressCntEL0Base;\r
+ UINT64 PhysicalAddressCntEL0Base;\r
\r
/// The physical timer interrupt\r
- UINT32 PhysicalTimerGSIV;\r
+ UINT32 PhysicalTimerGSIV;\r
\r
/** The physical timer flags as described by the GT Block\r
Timer frame Structure in the ACPI Specification.\r
*/\r
- UINT32 PhysicalTimerFlags;\r
+ UINT32 PhysicalTimerFlags;\r
\r
/// The virtual timer interrupt\r
- UINT32 VirtualTimerGSIV;\r
+ UINT32 VirtualTimerGSIV;\r
\r
/** The virtual timer flags as described by the GT Block\r
Timer frame Structure in the ACPI Specification.\r
*/\r
- UINT32 VirtualTimerFlags;\r
+ UINT32 VirtualTimerFlags;\r
\r
/** The common timer flags as described by the GT Block\r
Timer frame Structure in the ACPI Specification.\r
*/\r
- UINT32 CommonFlags;\r
+ UINT32 CommonFlags;\r
} CM_ARM_GTBLOCK_TIMER_FRAME_INFO;\r
\r
/** A structure that describes the\r
*/\r
typedef struct CmArmGTBlockInfo {\r
/// The physical base address for the GT Block Timer structure\r
- UINT64 GTBlockPhysicalAddress;\r
+ UINT64 GTBlockPhysicalAddress;\r
\r
/// The number of timer frames implemented in the GT Block\r
- UINT32 GTBlockTimerFrameCount;\r
+ UINT32 GTBlockTimerFrameCount;\r
\r
/// Reference token for the GT Block timer frame list\r
- CM_OBJECT_TOKEN GTBlockTimerFrameToken;\r
+ CM_OBJECT_TOKEN GTBlockTimerFrameToken;\r
} CM_ARM_GTBLOCK_INFO;\r
\r
/** A structure that describes the\r
- SBSA Generic Watchdog information for the Platform.\r
+ Arm Generic Watchdog information for the Platform.\r
\r
ID: EArmObjPlatformGenericWatchdogInfo\r
*/\r
typedef struct CmArmGenericWatchdogInfo {\r
- /// The physical base address of the SBSA Watchdog control frame\r
- UINT64 ControlFrameAddress;\r
+ /// The physical base address of the Arm Watchdog control frame\r
+ UINT64 ControlFrameAddress;\r
\r
- /// The physical base address of the SBSA Watchdog refresh frame\r
- UINT64 RefreshFrameAddress;\r
+ /// The physical base address of the Arm Watchdog refresh frame\r
+ UINT64 RefreshFrameAddress;\r
\r
/// The watchdog interrupt\r
- UINT32 TimerGSIV;\r
+ UINT32 TimerGSIV;\r
\r
- /** The flags for the watchdog as described by the SBSA watchdog\r
+ /** The flags for the watchdog as described by the Arm watchdog\r
structure in the ACPI specification.\r
*/\r
- UINT32 Flags;\r
+ UINT32 Flags;\r
} CM_ARM_GENERIC_WATCHDOG_INFO;\r
\r
/** A structure that describes the\r
*/\r
typedef struct CmArmPciConfigSpaceInfo {\r
/// The physical base address for the PCI segment\r
- UINT64 BaseAddress;\r
+ UINT64 BaseAddress;\r
\r
/// The PCI segment group number\r
- UINT16 PciSegmentGroupNumber;\r
+ UINT16 PciSegmentGroupNumber;\r
\r
/// The start bus number\r
- UINT8 StartBusNumber;\r
+ UINT8 StartBusNumber;\r
\r
/// The end bus number\r
- UINT8 EndBusNumber;\r
+ UINT8 EndBusNumber;\r
} CM_ARM_PCI_CONFIG_SPACE_INFO;\r
\r
/** A structure that describes the\r
*/\r
typedef struct CmArmHypervisorVendorId {\r
/// The hypervisor Vendor ID\r
- UINT64 HypervisorVendorId;\r
+ UINT64 HypervisorVendorId;\r
} CM_ARM_HYPERVISOR_VENDOR_ID;\r
\r
/** A structure that describes the\r
*/\r
typedef struct CmArmFixedFeatureFlags {\r
/// The Fixed feature flags\r
- UINT32 Flags;\r
+ UINT32 Flags;\r
} CM_ARM_FIXED_FEATURE_FLAGS;\r
\r
/** A structure that describes the\r
*/\r
typedef struct CmArmItsGroupNode {\r
/// An unique token used to identify this object\r
- CM_OBJECT_TOKEN Token;\r
+ CM_OBJECT_TOKEN Token;\r
/// The number of ITS identifiers in the ITS node\r
- UINT32 ItsIdCount;\r
+ UINT32 ItsIdCount;\r
/// Reference token for the ITS identifier array\r
- CM_OBJECT_TOKEN ItsIdToken;\r
+ CM_OBJECT_TOKEN ItsIdToken;\r
} CM_ARM_ITS_GROUP_NODE;\r
\r
/** A structure that describes the\r
*/\r
typedef struct CmArmNamedComponentNode {\r
/// An unique token used to identify this object\r
- CM_OBJECT_TOKEN Token;\r
+ CM_OBJECT_TOKEN Token;\r
/// Number of ID mappings\r
- UINT32 IdMappingCount;\r
+ UINT32 IdMappingCount;\r
/// Reference token for the ID mapping array\r
- CM_OBJECT_TOKEN IdMappingToken;\r
+ CM_OBJECT_TOKEN IdMappingToken;\r
\r
/// Flags for the named component\r
- UINT32 Flags;\r
+ UINT32 Flags;\r
\r
/// Memory access properties : Cache coherent attributes\r
- UINT32 CacheCoherent;\r
+ UINT32 CacheCoherent;\r
/// Memory access properties : Allocation hints\r
- UINT8 AllocationHints;\r
+ UINT8 AllocationHints;\r
/// Memory access properties : Memory access flags\r
- UINT8 MemoryAccessFlags;\r
+ UINT8 MemoryAccessFlags;\r
\r
/// Memory access properties : Address size limit\r
- UINT8 AddressSizeLimit;\r
+ UINT8 AddressSizeLimit;\r
+\r
/** ASCII Null terminated string with the full path to\r
the entry in the namespace for this object.\r
*/\r
- CHAR8* ObjectName;\r
+ CHAR8 *ObjectName;\r
} CM_ARM_NAMED_COMPONENT_NODE;\r
\r
/** A structure that describes the\r
*/\r
typedef struct CmArmRootComplexNode {\r
/// An unique token used to identify this object\r
- CM_OBJECT_TOKEN Token;\r
+ CM_OBJECT_TOKEN Token;\r
/// Number of ID mappings\r
- UINT32 IdMappingCount;\r
+ UINT32 IdMappingCount;\r
/// Reference token for the ID mapping array\r
- CM_OBJECT_TOKEN IdMappingToken;\r
+ CM_OBJECT_TOKEN IdMappingToken;\r
\r
/// Memory access properties : Cache coherent attributes\r
- UINT32 CacheCoherent;\r
+ UINT32 CacheCoherent;\r
/// Memory access properties : Allocation hints\r
- UINT8 AllocationHints;\r
+ UINT8 AllocationHints;\r
/// Memory access properties : Memory access flags\r
- UINT8 MemoryAccessFlags;\r
+ UINT8 MemoryAccessFlags;\r
\r
/// ATS attributes\r
- UINT32 AtsAttribute;\r
+ UINT32 AtsAttribute;\r
/// PCI segment number\r
- UINT32 PciSegmentNumber;\r
+ UINT32 PciSegmentNumber;\r
/// Memory address size limit\r
- UINT8 MemoryAddressSize;\r
+ UINT8 MemoryAddressSize;\r
} CM_ARM_ROOT_COMPLEX_NODE;\r
\r
/** A structure that describes the\r
*/\r
typedef struct CmArmSmmuV1SmmuV2Node {\r
/// An unique token used to identify this object\r
- CM_OBJECT_TOKEN Token;\r
+ CM_OBJECT_TOKEN Token;\r
/// Number of ID mappings\r
- UINT32 IdMappingCount;\r
+ UINT32 IdMappingCount;\r
/// Reference token for the ID mapping array\r
- CM_OBJECT_TOKEN IdMappingToken;\r
+ CM_OBJECT_TOKEN IdMappingToken;\r
\r
/// SMMU Base Address\r
- UINT64 BaseAddress;\r
+ UINT64 BaseAddress;\r
/// Length of the memory range covered by the SMMU\r
- UINT64 Span;\r
+ UINT64 Span;\r
/// SMMU Model\r
- UINT32 Model;\r
+ UINT32 Model;\r
/// SMMU flags\r
- UINT32 Flags;\r
+ UINT32 Flags;\r
\r
/// Number of context interrupts\r
- UINT32 ContextInterruptCount;\r
+ UINT32 ContextInterruptCount;\r
/// Reference token for the context interrupt array\r
- CM_OBJECT_TOKEN ContextInterruptToken;\r
+ CM_OBJECT_TOKEN ContextInterruptToken;\r
\r
/// Number of PMU interrupts\r
- UINT32 PmuInterruptCount;\r
+ UINT32 PmuInterruptCount;\r
/// Reference token for the PMU interrupt array\r
- CM_OBJECT_TOKEN PmuInterruptToken;\r
+ CM_OBJECT_TOKEN PmuInterruptToken;\r
\r
/// GSIV of the SMMU_NSgIrpt interrupt\r
- UINT32 SMMU_NSgIrpt;\r
+ UINT32 SMMU_NSgIrpt;\r
/// SMMU_NSgIrpt interrupt flags\r
- UINT32 SMMU_NSgIrptFlags;\r
+ UINT32 SMMU_NSgIrptFlags;\r
/// GSIV of the SMMU_NSgCfgIrpt interrupt\r
- UINT32 SMMU_NSgCfgIrpt;\r
+ UINT32 SMMU_NSgCfgIrpt;\r
/// SMMU_NSgCfgIrpt interrupt flags\r
- UINT32 SMMU_NSgCfgIrptFlags;\r
+ UINT32 SMMU_NSgCfgIrptFlags;\r
} CM_ARM_SMMUV1_SMMUV2_NODE;\r
\r
/** A structure that describes the\r
*/\r
typedef struct CmArmSmmuV3Node {\r
/// An unique token used to identify this object\r
- CM_OBJECT_TOKEN Token;\r
+ CM_OBJECT_TOKEN Token;\r
/// Number of ID mappings\r
- UINT32 IdMappingCount;\r
+ UINT32 IdMappingCount;\r
/// Reference token for the ID mapping array\r
- CM_OBJECT_TOKEN IdMappingToken;\r
+ CM_OBJECT_TOKEN IdMappingToken;\r
\r
/// SMMU Base Address\r
- UINT64 BaseAddress;\r
+ UINT64 BaseAddress;\r
/// SMMU flags\r
- UINT32 Flags;\r
+ UINT32 Flags;\r
/// VATOS address\r
- UINT64 VatosAddress;\r
+ UINT64 VatosAddress;\r
/// Model\r
- UINT32 Model;\r
+ UINT32 Model;\r
/// GSIV of the Event interrupt if SPI based\r
- UINT32 EventInterrupt;\r
+ UINT32 EventInterrupt;\r
/// PRI Interrupt if SPI based\r
- UINT32 PriInterrupt;\r
+ UINT32 PriInterrupt;\r
/// GERR interrupt if GSIV based\r
- UINT32 GerrInterrupt;\r
+ UINT32 GerrInterrupt;\r
/// Sync interrupt if GSIV based\r
- UINT32 SyncInterrupt;\r
+ UINT32 SyncInterrupt;\r
\r
/// Proximity domain flag\r
- UINT32 ProximityDomain;\r
+ UINT32 ProximityDomain;\r
/// Index into the array of ID mapping\r
- UINT32 DeviceIdMappingIndex;\r
+ UINT32 DeviceIdMappingIndex;\r
} CM_ARM_SMMUV3_NODE;\r
\r
/** A structure that describes the\r
*/\r
typedef struct CmArmPmcgNode {\r
/// An unique token used to identify this object\r
- CM_OBJECT_TOKEN Token;\r
+ CM_OBJECT_TOKEN Token;\r
/// Number of ID mappings\r
- UINT32 IdMappingCount;\r
+ UINT32 IdMappingCount;\r
/// Reference token for the ID mapping array\r
- CM_OBJECT_TOKEN IdMappingToken;\r
+ CM_OBJECT_TOKEN IdMappingToken;\r
\r
/// Base Address for performance monitor counter group\r
- UINT64 BaseAddress;\r
+ UINT64 BaseAddress;\r
/// GSIV for the Overflow interrupt\r
- UINT32 OverflowInterrupt;\r
+ UINT32 OverflowInterrupt;\r
/// Page 1 Base address\r
- UINT64 Page1BaseAddress;\r
+ UINT64 Page1BaseAddress;\r
\r
/// Reference token for the IORT node associated with this node\r
- CM_OBJECT_TOKEN ReferenceToken;\r
+ CM_OBJECT_TOKEN ReferenceToken;\r
} CM_ARM_PMCG_NODE;\r
\r
/** A structure that describes the\r
*/\r
typedef struct CmArmGicItsIdentifier {\r
/// The ITS Identifier\r
- UINT32 ItsId;\r
+ UINT32 ItsId;\r
} CM_ARM_ITS_IDENTIFIER;\r
\r
/** A structure that describes the\r
*/\r
typedef struct CmArmIdMapping {\r
/// Input base\r
- UINT32 InputBase;\r
+ UINT32 InputBase;\r
/// Number of input IDs\r
- UINT32 NumIds;\r
+ UINT32 NumIds;\r
/// Output Base\r
- UINT32 OutputBase;\r
+ UINT32 OutputBase;\r
/// Reference token for the output node\r
- CM_OBJECT_TOKEN OutputReferenceToken;\r
+ CM_OBJECT_TOKEN OutputReferenceToken;\r
/// Flags\r
- UINT32 Flags;\r
+ UINT32 Flags;\r
} CM_ARM_ID_MAPPING;\r
\r
/** A structure that describes the Arm\r
Vector Flags (Byte 3) of the Extended Interrupt\r
resource descriptor.\r
See EFI_ACPI_EXTENDED_INTERRUPT_FLAG_xxx in Acpi10.h\r
-\r
- ID: EArmObjExtendedInterruptInfo\r
*/\r
typedef CM_ARM_GENERIC_INTERRUPT CM_ARM_EXTENDED_INTERRUPT;\r
\r
*/\r
typedef struct CmArmProcHierarchyInfo {\r
/// A unique token used to identify this object\r
- CM_OBJECT_TOKEN Token;\r
+ CM_OBJECT_TOKEN Token;\r
/// Processor structure flags (ACPI 6.3 - January 2019, PPTT, Table 5-155)\r
- UINT32 Flags;\r
+ UINT32 Flags;\r
/// Token for the parent CM_ARM_PROC_HIERARCHY_INFO object in the processor\r
/// topology. A value of CM_NULL_TOKEN means this node has no parent.\r
- CM_OBJECT_TOKEN ParentToken;\r
+ CM_OBJECT_TOKEN ParentToken;\r
/// Token of the associated CM_ARM_GICC_INFO object which has the\r
/// corresponding ACPI Processor ID. A value of CM_NULL_TOKEN means this\r
/// node represents a group of associated processors and it does not have an\r
/// associated GIC CPU interface.\r
- CM_OBJECT_TOKEN GicCToken;\r
+ CM_OBJECT_TOKEN GicCToken;\r
/// Number of resources private to this Node\r
- UINT32 NoOfPrivateResources;\r
+ UINT32 NoOfPrivateResources;\r
/// Token of the array which contains references to the resources private to\r
/// this CM_ARM_PROC_HIERARCHY_INFO instance. This field is ignored if\r
/// the NoOfPrivateResources is 0, in which case it is recommended to set\r
/// this field to CM_NULL_TOKEN.\r
- CM_OBJECT_TOKEN PrivateResourcesArrayToken;\r
+ CM_OBJECT_TOKEN PrivateResourcesArrayToken;\r
+ /// Optional field: Reference Token for the Lpi state of this processor.\r
+ /// Token identifying a CM_ARM_OBJ_REF structure, itself referencing\r
+ /// CM_ARM_LPI_INFO objects.\r
+ CM_OBJECT_TOKEN LpiToken;\r
} CM_ARM_PROC_HIERARCHY_INFO;\r
\r
/** A structure that describes the Cache Type Structure (Type 1) in PPTT\r
*/\r
typedef struct CmArmCacheInfo {\r
/// A unique token used to identify this object\r
- CM_OBJECT_TOKEN Token;\r
+ CM_OBJECT_TOKEN Token;\r
/// Reference token for the next level of cache that is private to the same\r
/// CM_ARM_PROC_HIERARCHY_INFO instance. A value of CM_NULL_TOKEN means this\r
/// entry represents the last cache level appropriate to the processor\r
/// hierarchy node structures using this entry.\r
- CM_OBJECT_TOKEN NextLevelOfCacheToken;\r
+ CM_OBJECT_TOKEN NextLevelOfCacheToken;\r
/// Size of the cache in bytes\r
- UINT32 Size;\r
+ UINT32 Size;\r
/// Number of sets in the cache\r
- UINT32 NumberOfSets;\r
+ UINT32 NumberOfSets;\r
/// Integer number of ways. The maximum associativity supported by\r
/// ACPI Cache type structure is limited to MAX_UINT8. However,\r
/// the maximum number of ways supported by the architecture is\r
/// PPTT_ARM_CCIDX_CACHE_ASSOCIATIVITY_MAX. Therfore this field\r
/// is 32-bit wide.\r
- UINT32 Associativity;\r
- /// Cache attributes (ACPI 6.3 - January 2019, PPTT, Table 5-156)\r
- UINT8 Attributes;\r
+ UINT32 Associativity;\r
+ /// Cache attributes (ACPI 6.4 - January 2021, PPTT, Table 5.140)\r
+ UINT8 Attributes;\r
/// Line size in bytes\r
- UINT16 LineSize;\r
+ UINT16 LineSize;\r
+ /// Unique ID for the cache\r
+ UINT32 CacheId;\r
} CM_ARM_CACHE_INFO;\r
\r
-/** A structure that describes the ID Structure (Type 2) in PPTT\r
-\r
- ID: EArmObjProcNodeIdInfo\r
-*/\r
-typedef struct CmArmProcNodeIdInfo {\r
- /// A unique token used to identify this object\r
- CM_OBJECT_TOKEN Token;\r
- // Vendor ID (as described in ACPI ID registry)\r
- UINT32 VendorId;\r
- /// First level unique node ID\r
- UINT64 Level1Id;\r
- /// Second level unique node ID\r
- UINT64 Level2Id;\r
- /// Major revision of the node\r
- UINT16 MajorRev;\r
- /// Minor revision of the node\r
- UINT16 MinorRev;\r
- /// Spin revision of the node\r
- UINT16 SpinRev;\r
-} CM_ARM_PROC_NODE_ID_INFO;\r
-\r
/** A structure that describes a reference to another Configuration Manager\r
object.\r
\r
*/\r
typedef struct CmArmObjRef {\r
/// Token of the CM object being referenced\r
- CM_OBJECT_TOKEN ReferenceToken;\r
+ CM_OBJECT_TOKEN ReferenceToken;\r
} CM_ARM_OBJ_REF;\r
\r
/** A structure that describes the Memory Affinity Structure (Type 1) in SRAT\r
*/\r
typedef struct CmArmMemoryAffinityInfo {\r
/// The proximity domain to which the "range of memory" belongs.\r
- UINT32 ProximityDomain;\r
+ UINT32 ProximityDomain;\r
\r
/// Base Address\r
- UINT64 BaseAddress;\r
+ UINT64 BaseAddress;\r
\r
/// Length\r
- UINT64 Length;\r
+ UINT64 Length;\r
\r
/// Flags\r
- UINT32 Flags;\r
+ UINT32 Flags;\r
} CM_ARM_MEMORY_AFFINITY_INFO;\r
\r
/** A structure that describes the ACPI Device Handle (Type 0) in the\r
*/\r
typedef struct CmArmDeviceHandleAcpi {\r
/// Hardware ID\r
- UINT64 Hid;\r
+ UINT64 Hid;\r
\r
/// Unique Id\r
- UINT32 Uid;\r
+ UINT32 Uid;\r
} CM_ARM_DEVICE_HANDLE_ACPI;\r
\r
/** A structure that describes the PCI Device Handle (Type 1) in the\r
*/\r
typedef struct CmArmDeviceHandlePci {\r
/// PCI Segment Number\r
- UINT16 SegmentNumber;\r
+ UINT16 SegmentNumber;\r
\r
/// PCI Bus Number - Max 256 busses (Bits 15:8 of BDF)\r
- UINT8 BusNumber;\r
+ UINT8 BusNumber;\r
\r
/// PCI Device Number - Max 32 devices (Bits 7:3 of BDF)\r
- UINT8 DeviceNumber;\r
+ UINT8 DeviceNumber;\r
\r
/// PCI Function Number - Max 8 functions (Bits 2:0 of BDF)\r
- UINT8 FunctionNumber;\r
+ UINT8 FunctionNumber;\r
} CM_ARM_DEVICE_HANDLE_PCI;\r
\r
/** A structure that describes the Generic Initiator Affinity structure in SRAT\r
*/\r
typedef struct CmArmGenericInitiatorAffinityInfo {\r
/// The proximity domain to which the generic initiator belongs.\r
- UINT32 ProximityDomain;\r
+ UINT32 ProximityDomain;\r
\r
/// Flags\r
- UINT32 Flags;\r
+ UINT32 Flags;\r
\r
/// Device Handle Type\r
- UINT8 DeviceHandleType;\r
+ UINT8 DeviceHandleType;\r
\r
/// Reference Token for the Device Handle\r
- CM_OBJECT_TOKEN DeviceHandleToken;\r
+ CM_OBJECT_TOKEN DeviceHandleToken;\r
} CM_ARM_GENERIC_INITIATOR_AFFINITY_INFO;\r
\r
/** A structure that describes the CMN-600 hardware.\r
typedef struct CmArmCmn600Info {\r
/// The PERIPHBASE address.\r
/// Corresponds to the Configuration Node Region (CFGR) base address.\r
- UINT64 PeriphBaseAddress;\r
+ UINT64 PeriphBaseAddress;\r
\r
/// The PERIPHBASE address length.\r
/// Corresponds to the CFGR base address length.\r
- UINT64 PeriphBaseAddressLength;\r
+ UINT64 PeriphBaseAddressLength;\r
\r
/// The ROOTNODEBASE address.\r
/// Corresponds to the Root node (ROOT) base address.\r
- UINT64 RootNodeBaseAddress;\r
+ UINT64 RootNodeBaseAddress;\r
\r
/// The Debug and Trace Logic Controller (DTC) count.\r
/// CMN-600 can have maximum 4 DTCs.\r
- UINT8 DtcCount;\r
+ UINT8 DtcCount;\r
\r
/// DTC Interrupt list.\r
/// The first interrupt resource descriptor pertains to\r
/// and DtcInterrupt[3] are ignored.\r
/// Note: The size of CM_ARM_CMN_600_INFO structure remains\r
/// constant and does not vary with the DTC count.\r
- CM_ARM_EXTENDED_INTERRUPT DtcInterrupt[4];\r
+ CM_ARM_EXTENDED_INTERRUPT DtcInterrupt[4];\r
} CM_ARM_CMN_600_INFO;\r
\r
+/** A structure that describes the Lpi information.\r
+\r
+ The Low Power Idle states are described in DSDT/SSDT and associated\r
+ to cpus/clusters in the cpu topology.\r
+\r
+ ID: EArmObjLpiInfo\r
+*/\r
+typedef struct CmArmLpiInfo {\r
+ /** Minimum Residency. Time in microseconds after which a\r
+ state becomes more energy efficient than any shallower state.\r
+ */\r
+ UINT32 MinResidency;\r
+\r
+ /** Worst case time in microseconds from a wake interrupt\r
+ being asserted to the return to a running state\r
+ */\r
+ UINT32 WorstCaseWakeLatency;\r
+\r
+ /** Flags.\r
+ */\r
+ UINT32 Flags;\r
+\r
+ /** Architecture specific context loss flags.\r
+ */\r
+ UINT32 ArchFlags;\r
+\r
+ /** Residency counter frequency in cycles-per-second (Hz).\r
+ */\r
+ UINT32 ResCntFreq;\r
+\r
+ /** Every shallower power state in the parent is also enabled.\r
+ */\r
+ UINT32 EnableParentState;\r
+\r
+ /** The EntryMethod _LPI field can be described as an integer\r
+ or in a Register resource data descriptor.\r
+\r
+ If IsInteger is TRUE, the IntegerEntryMethod field is used.\r
+ If IsInteger is FALSE, the RegisterEntryMethod field is used.\r
+ */\r
+ BOOLEAN IsInteger;\r
+\r
+ /** EntryMethod described as an Integer.\r
+ */\r
+ UINT64 IntegerEntryMethod;\r
+\r
+ /** EntryMethod described as a EFI_ACPI_GENERIC_REGISTER_DESCRIPTOR.\r
+ */\r
+ EFI_ACPI_6_3_GENERIC_ADDRESS_STRUCTURE RegisterEntryMethod;\r
+\r
+ /** Residency counter register.\r
+ */\r
+ EFI_ACPI_6_3_GENERIC_ADDRESS_STRUCTURE ResidencyCounterRegister;\r
+\r
+ /** Usage counter register.\r
+ */\r
+ EFI_ACPI_6_3_GENERIC_ADDRESS_STRUCTURE UsageCounterRegister;\r
+\r
+ /** String representing the Lpi state\r
+ */\r
+ CHAR8 StateName[16];\r
+} CM_ARM_LPI_INFO;\r
+\r
#pragma pack()\r
\r
#endif // ARM_NAMESPACE_OBJECTS_H_\r
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