/** @file\r
Header file for IDE Bus Driver's Data Structures\r
\r
- Copyright (c) 2006 - 2007 Intel Corporation. <BR>\r
- All rights reserved. This program and the accompanying materials \r
- are licensed and made available under the terms and conditions of the BSD License \r
- which accompanies this distribution. The full text of the license may be found at \r
- http://opensource.org/licenses/bsd-license.php \r
+ Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>\r
+ This program and the accompanying materials\r
+ are licensed and made available under the terms and conditions of the BSD License\r
+ which accompanies this distribution. The full text of the license may be found at\r
+ http://opensource.org/licenses/bsd-license.php\r
\r
- THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r
- WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
\r
**/\r
\r
typedef union {\r
UINT16 AltStatus; /* when read */\r
UINT16 DeviceControl; /* when write */\r
-} IDE_AltStatus_OR_DeviceControl;\r
+} IDE_ALTSTATUS_OR_DEVICECONTROL;\r
\r
//\r
// IDE registers set\r
UINT16 Head;\r
IDE_CMD_OR_STATUS Reg;\r
\r
- IDE_AltStatus_OR_DeviceControl Alt;\r
+ IDE_ALTSTATUS_OR_DEVICECONTROL Alt;\r
UINT16 DriveAddress;\r
\r
UINT16 MasterSlave;\r
//\r
// Bus Master Reg\r
//\r
-#define BMIC_nREAD BIT3\r
+#define BMIC_NREAD BIT3\r
#define BMIC_START BIT0\r
#define BMIS_INTERRUPT BIT2\r
#define BMIS_ERROR BIT1\r
//\r
// 1 second\r
//\r
-#define ATATIMEOUT 1000 \r
+#define ATATIMEOUT 1000\r
\r
//\r
// ATAPITIMEOUT is used for waiting operation\r
//\r
// 1 second\r
//\r
-#define ATAPITIMEOUT 1000 \r
+#define ATAPITIMEOUT 1000\r
\r
//\r
// ATAPILONGTIMEOUT is used for waiting read and\r
//\r
// 2 seconds\r
//\r
-#define CDROMLONGTIMEOUT 2000 \r
+#define CDROMLONGTIMEOUT 2000\r
\r
//\r
// 5 seconds\r
//\r
-#define ATAPILONGTIMEOUT 5000 \r
+#define ATAPILONGTIMEOUT 5000\r
\r
//\r
// 10 seconds\r
#define SETFEATURE TRUE\r
#define CLEARFEATURE FALSE\r
\r
-//\r
-// PIO mode definition\r
-//\r
-typedef enum {\r
- ATA_PIO_MODE_BELOW_2,\r
- ATA_PIO_MODE_2,\r
- ATA_PIO_MODE_3,\r
- ATA_PIO_MODE_4\r
+///\r
+/// PIO mode definition\r
+///\r
+typedef enum _ATA_PIO_MODE_ {\r
+ AtaPioModeBelow2,\r
+ AtaPioMode2,\r
+ AtaPioMode3,\r
+ AtaPioMode4\r
} ATA_PIO_MODE;\r
\r
//\r
// Multi word DMA definition\r
//\r
-typedef enum {\r
- ATA_MDMA_MODE_0,\r
- ATA_MDMA_MODE_1,\r
- ATA_MDMA_MODE_2\r
+typedef enum _ATA_MDMA_MODE_ {\r
+ AtaMdmaMode0,\r
+ AtaMdmaMode1,\r
+ AtaMdmaMode2\r
} ATA_MDMA_MODE;\r
\r
//\r
// UDMA mode definition\r
//\r
-typedef enum {\r
- ATA_UDMA_MODE_0,\r
- ATA_UDMA_MODE_1,\r
- ATA_UDMA_MODE_2,\r
- ATA_UDMA_MODE_3,\r
- ATA_UDMA_MODE_4,\r
- ATA_UDMA_MODE_5\r
+typedef enum _ATA_UDMA_MODE_ {\r
+ AtaUdmaMode0,\r
+ AtaUdmaMode1,\r
+ AtaUdmaMode2,\r
+ AtaUdmaMode3,\r
+ AtaUdmaMode4,\r
+ AtaUdmaMode5\r
} ATA_UDMA_MODE;\r
\r
#define ATA_MODE_CATEGORY_DEFAULT_PIO 0x00\r