/** @file\r
+ PCI emumeration support functions implementation for PCI Bus module.\r
\r
-Copyright (c) 2006, Intel Corporation\r
+Copyright (c) 2006 - 2009, Intel Corporation\r
All rights reserved. This program and the accompanying materials\r
are licensed and made available under the terms and conditions of the BSD License\r
which accompanies this distribution. The full text of the license may be found at\r
\r
**/\r
\r
-\r
#include "PciBus.h"\r
-#include "PciEnumeratorSupport.h"\r
-#include "PciCommand.h"\r
-#include "PciIo.h"\r
\r
/**\r
This routine is used to check whether the pci device is present.\r
- \r
+\r
@param PciRootBridgeIo Pointer to instance of EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.\r
- @param Pci Output buffer for PCI device structure.\r
+ @param Pci Output buffer for PCI device configuration space.\r
@param Bus PCI bus NO.\r
@param Device PCI device NO.\r
@param Func PCI Func NO.\r
- \r
- @retval EFI_NOT_FOUND device not present.\r
- @retval EFI_SUCCESS device is found.\r
+\r
+ @retval EFI_NOT_FOUND PCI device not present.\r
+ @retval EFI_SUCCESS PCI device is found.\r
+\r
**/\r
EFI_STATUS\r
PciDevicePresent (\r
- IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *PciRootBridgeIo,\r
- PCI_TYPE00 *Pci,\r
- UINT8 Bus,\r
- UINT8 Device,\r
- UINT8 Func\r
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *PciRootBridgeIo,\r
+ OUT PCI_TYPE00 *Pci,\r
+ IN UINT8 Bus,\r
+ IN UINT8 Device,\r
+ IN UINT8 Func\r
)\r
{\r
UINT64 Address;\r
Address = EFI_PCI_ADDRESS (Bus, Device, Func, 0);\r
\r
//\r
- // Read the Vendor Id register\r
+ // Read the Vendor ID register\r
//\r
- Status = PciRootBridgeIoRead (\r
+ Status = PciRootBridgeIo->Pci.Read (\r
PciRootBridgeIo,\r
- NULL,\r
EfiPciWidthUint32,\r
Address,\r
1,\r
);\r
\r
if (!EFI_ERROR (Status) && (Pci->Hdr).VendorId != 0xffff) {\r
-\r
//\r
// Read the entire config header for the device\r
//\r
-\r
- Status = PciRootBridgeIoRead (\r
+ Status = PciRootBridgeIo->Pci.Read (\r
PciRootBridgeIo,\r
- NULL,\r
EfiPciWidthUint32,\r
Address,\r
sizeof (PCI_TYPE00) / sizeof (UINT32),\r
}\r
\r
/**\r
- Collect all the resource information under this root bridge\r
+ Collect all the resource information under this root bridge.\r
+\r
A database that records all the information about pci device subject to this\r
root bridge will then be created.\r
- \r
+\r
@param Bridge Parent bridge instance.\r
- @param StartBusNumber Bus number of begining. \r
+ @param StartBusNumber Bus number of begining.\r
+\r
+ @retval EFI_SUCCESS PCI device is found.\r
+ @retval other Some error occurred when reading PCI bridge information.\r
+\r
**/\r
EFI_STATUS\r
PciPciDeviceInfoCollector (\r
IN PCI_IO_DEVICE *Bridge,\r
- UINT8 StartBusNumber\r
+ IN UINT8 StartBusNumber\r
)\r
{\r
EFI_STATUS Status;\r
//\r
// Check to see whether PCI device is present\r
//\r
-\r
Status = PciDevicePresent (\r
- Bridge->PciRootBridgeIo,\r
- &Pci,\r
- (UINT8) StartBusNumber,\r
- (UINT8) Device,\r
- (UINT8) Func\r
- );\r
-\r
+ Bridge->PciRootBridgeIo,\r
+ &Pci,\r
+ (UINT8) StartBusNumber,\r
+ (UINT8) Device,\r
+ (UINT8) Func\r
+ );\r
if (!EFI_ERROR (Status)) {\r
\r
//\r
// Collect all the information about the PCI device discovered\r
//\r
Status = PciSearchDevice (\r
- Bridge,\r
- &Pci,\r
- (UINT8) StartBusNumber,\r
- Device,\r
- Func,\r
- &PciIoDevice\r
- );\r
+ Bridge,\r
+ &Pci,\r
+ (UINT8) StartBusNumber,\r
+ Device,\r
+ Func,\r
+ &PciIoDevice\r
+ );\r
\r
//\r
// Recursively scan PCI busses on the other side of PCI-PCI bridges\r
//\r
//\r
-\r
if (!EFI_ERROR (Status) && (IS_PCI_BRIDGE (&Pci) || IS_CARDBUS_BRIDGE (&Pci))) {\r
\r
//\r
//\r
PciIo = &(PciIoDevice->PciIo);\r
\r
- Status = PciIoRead (PciIo, EfiPciIoWidthUint8, 0x19, 1, &SecBus);\r
+ Status = PciIo->Pci.Read (PciIo, EfiPciIoWidthUint8, PCI_BRIDGE_SECONDARY_BUS_REGISTER_OFFSET, 1, &SecBus);\r
\r
if (EFI_ERROR (Status)) {\r
return Status;\r
// Deep enumerate the next level bus\r
//\r
Status = PciPciDeviceInfoCollector (\r
- PciIoDevice,\r
- (UINT8) (SecBus)\r
- );\r
+ PciIoDevice,\r
+ (UINT8) (SecBus)\r
+ );\r
\r
}\r
\r
}\r
\r
/**\r
- Seach required device and get PCI device info block\r
- \r
+ Seach required device and create PCI device instance.\r
+\r
@param Bridge Parent bridge instance.\r
- @param Pci Output of PCI device info block.\r
+ @param Pci Input PCI device information block.\r
@param Bus PCI bus NO.\r
@param Device PCI device NO.\r
@param Func PCI func NO.\r
- @param PciDevice output of searched PCI device instance.\r
+ @param PciDevice Output of searched PCI device instance.\r
+\r
+ @retval EFI_SUCCESS Successfully created PCI device instance.\r
+ @retval EFI_OUT_OF_RESOURCES Cannot get PCI device information.\r
+\r
**/\r
EFI_STATUS\r
PciSearchDevice (\r
}\r
\r
/**\r
- Create PCI private data for PCI device\r
- \r
- @param Bridge Parent bridge instance.\r
- @param Pci PCI bar block\r
- @param Bus PCI device Bus NO.\r
- @param Device PCI device DeviceNO.\r
- @param Func PCI device's func NO.\r
- \r
- @return new PCI device's private date structure.\r
+ Create PCI device instance for PCI device.\r
+\r
+ @param Bridge Parent bridge instance.\r
+ @param Pci Input PCI device information block.\r
+ @param Bus PCI device Bus NO.\r
+ @param Device PCI device Device NO.\r
+ @param Func PCI device's func NO.\r
+\r
+ @return Created PCI device instance.\r
+\r
**/\r
PCI_IO_DEVICE *\r
GatherDeviceInfo (\r
IN PCI_IO_DEVICE *Bridge,\r
IN PCI_TYPE00 *Pci,\r
- UINT8 Bus,\r
- UINT8 Device,\r
- UINT8 Func\r
+ IN UINT8 Bus,\r
+ IN UINT8 Device,\r
+ IN UINT8 Func\r
)\r
{\r
UINTN Offset;\r
//\r
if (gFullEnumeration) {\r
\r
- PciDisableCommandRegister (PciIoDevice, EFI_PCI_COMMAND_BITS_OWNED);\r
+ PCI_DISABLE_COMMAND_REGISTER (PciIoDevice, EFI_PCI_COMMAND_BITS_OWNED);\r
\r
}\r
\r
//\r
// Start to parse the bars\r
//\r
- for (Offset = 0x10, BarIndex = 0; Offset <= 0x24; BarIndex++) {\r
+ for (Offset = 0x10, BarIndex = 0; Offset <= 0x24 && BarIndex < PCI_MAX_BAR; BarIndex++) {\r
Offset = PciParseBar (PciIoDevice, Offset, BarIndex);\r
}\r
\r
}\r
\r
/**\r
- Create private data for bridge device's PPB.\r
- \r
- @param Bridge Parent bridge \r
- @param Pci Pci device block\r
- @param Bus Bridge device's bus NO.\r
- @param Device Bridge device's device NO.\r
- @param Func Bridge device's func NO.\r
- \r
- @return bridge device instance.\r
+ Create PCI device instance for PCI-PCI bridge.\r
+\r
+ @param Bridge Parent bridge instance.\r
+ @param Pci Input PCI device information block.\r
+ @param Bus PCI device Bus NO.\r
+ @param Device PCI device Device NO.\r
+ @param Func PCI device's func NO.\r
+\r
+ @return Created PCI device instance.\r
+\r
**/\r
PCI_IO_DEVICE *\r
GatherPpbInfo (\r
IN PCI_IO_DEVICE *Bridge,\r
IN PCI_TYPE00 *Pci,\r
- UINT8 Bus,\r
- UINT8 Device,\r
- UINT8 Func\r
+ IN UINT8 Bus,\r
+ IN UINT8 Device,\r
+ IN UINT8 Func\r
)\r
{\r
EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *PciRootBridgeIo;\r
PCI_IO_DEVICE *PciIoDevice;\r
EFI_STATUS Status;\r
- UINT32 Value;\r
+ UINT8 Value;\r
EFI_PCI_IO_PROTOCOL *PciIo;\r
UINT8 Temp;\r
\r
);\r
\r
if (gFullEnumeration) {\r
- PciDisableCommandRegister (PciIoDevice, EFI_PCI_COMMAND_BITS_OWNED);\r
+ PCI_DISABLE_COMMAND_REGISTER (PciIoDevice, EFI_PCI_COMMAND_BITS_OWNED);\r
\r
//\r
// Initalize the bridge control register\r
//\r
- PciDisableBridgeControlRegister (PciIoDevice, EFI_PCI_BRIDGE_CONTROL_BITS_OWNED);\r
+ PCI_DISABLE_BRIDGE_CONTROL_REGISTER (PciIoDevice, EFI_PCI_BRIDGE_CONTROL_BITS_OWNED);\r
\r
}\r
\r
//\r
// Test whether it support 32 decode or not\r
//\r
- PciIoRead (PciIo, EfiPciIoWidthUint8, 0x1C, 1, &Temp);\r
- PciIoWrite (PciIo, EfiPciIoWidthUint8, 0x1C, 1, &gAllOne);\r
- PciIoRead (PciIo, EfiPciIoWidthUint8, 0x1C, 1, &Value);\r
- PciIoWrite (PciIo, EfiPciIoWidthUint8, 0x1C, 1, &Temp);\r
+ PciIo->Pci.Read (PciIo, EfiPciIoWidthUint8, 0x1C, 1, &Temp);\r
+ PciIo->Pci.Write (PciIo, EfiPciIoWidthUint8, 0x1C, 1, &gAllOne);\r
+ PciIo->Pci.Read (PciIo, EfiPciIoWidthUint8, 0x1C, 1, &Value);\r
+ PciIo->Pci.Write (PciIo, EfiPciIoWidthUint8, 0x1C, 1, &Temp);\r
\r
if (Value != 0) {\r
if ((Value & 0x01) != 0) {\r
);\r
\r
//\r
- // test if it supports 64 memory or not\r
+ // Test if it supports 64 memory or not\r
//\r
if (!EFI_ERROR (Status)) {\r
\r
return PciIoDevice;\r
}\r
\r
+\r
/**\r
- Create private data for hotplug bridge device\r
- \r
- @param Bridge Parent bridge instance\r
- @param Pci PCI bar block\r
- @param Bus hotplug bridge device's bus NO.\r
- @param Device hotplug bridge device's device NO.\r
- @param Func hotplug bridge device's Func NO.\r
- \r
- @return hotplug bridge device instance.\r
+ Create PCI device instance for PCI Card bridge device.\r
+\r
+ @param Bridge Parent bridge instance.\r
+ @param Pci Input PCI device information block.\r
+ @param Bus PCI device Bus NO.\r
+ @param Device PCI device Device NO.\r
+ @param Func PCI device's func NO.\r
+\r
+ @return Created PCI device instance.\r
+\r
**/\r
PCI_IO_DEVICE *\r
GatherP2CInfo (\r
IN PCI_IO_DEVICE *Bridge,\r
IN PCI_TYPE00 *Pci,\r
- UINT8 Bus,\r
- UINT8 Device,\r
- UINT8 Func\r
+ IN UINT8 Bus,\r
+ IN UINT8 Device,\r
+ IN UINT8 Func\r
)\r
{\r
EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *PciRootBridgeIo;\r
);\r
\r
if (gFullEnumeration) {\r
- PciDisableCommandRegister (PciIoDevice, EFI_PCI_COMMAND_BITS_OWNED);\r
+ PCI_DISABLE_COMMAND_REGISTER (PciIoDevice, EFI_PCI_COMMAND_BITS_OWNED);\r
\r
//\r
// Initalize the bridge control register\r
//\r
- PciDisableBridgeControlRegister (PciIoDevice, EFI_PCCARD_BRIDGE_CONTROL_BITS_OWNED);\r
-\r
+ PCI_DISABLE_BRIDGE_CONTROL_REGISTER (PciIoDevice, EFI_PCCARD_BRIDGE_CONTROL_BITS_OWNED);\r
}\r
+\r
//\r
// P2C only has one bar that is in 0x10\r
//\r
}\r
\r
/**\r
- Create device path for pci deivce\r
- \r
+ Create device path for pci deivce.\r
+\r
@param ParentDevicePath Parent bridge's path.\r
@param PciIoDevice Pci device instance.\r
- \r
- @return device path protocol instance for specific pci device.\r
+\r
+ @return Device path protocol instance for specific pci device.\r
+\r
**/\r
EFI_DEVICE_PATH_PROTOCOL *\r
CreatePciDevicePath (\r
}\r
\r
/**\r
- Check the bar is existed or not.\r
+ Check whether the bar is existed or not.\r
\r
- @param PciIoDevice - A pointer to the PCI_IO_DEVICE.\r
- @param Offset - The offset.\r
- @param BarLengthValue - The bar length value.\r
- @param OriginalBarValue - The original bar value.\r
+ @param PciIoDevice A pointer to the PCI_IO_DEVICE.\r
+ @param Offset The offset.\r
+ @param BarLengthValue The bar length value returned.\r
+ @param OriginalBarValue The original bar value returned.\r
\r
- @retval EFI_NOT_FOUND - The bar don't exist.\r
- @retval EFI_SUCCESS - The bar exist.\r
+ @retval EFI_NOT_FOUND The bar doesn't exist.\r
+ @retval EFI_SUCCESS The bar exist.\r
\r
**/\r
EFI_STATUS\r
BarExisted (\r
- IN PCI_IO_DEVICE *PciIoDevice,\r
- IN UINTN Offset,\r
- OUT UINT32 *BarLengthValue,\r
- OUT UINT32 *OriginalBarValue\r
+ IN PCI_IO_DEVICE *PciIoDevice,\r
+ IN UINTN Offset,\r
+ OUT UINT32 *BarLengthValue,\r
+ OUT UINT32 *OriginalBarValue\r
)\r
-\r
{\r
EFI_PCI_IO_PROTOCOL *PciIo;\r
UINT32 OriginalValue;\r
//\r
// Preserve the original value\r
//\r
-\r
- PciIoRead (PciIo, EfiPciIoWidthUint32, (UINT8) Offset, 1, &OriginalValue);\r
+ PciIo->Pci.Read (PciIo, EfiPciIoWidthUint32, (UINT8) Offset, 1, &OriginalValue);\r
\r
//\r
// Raise TPL to high level to disable timer interrupt while the BAR is probed\r
//\r
OldTpl = gBS->RaiseTPL (TPL_HIGH_LEVEL);\r
\r
- PciIoWrite (PciIo, EfiPciIoWidthUint32, (UINT8) Offset, 1, &gAllOne);\r
- PciIoRead (PciIo, EfiPciIoWidthUint32, (UINT8) Offset, 1, &Value);\r
+ PciIo->Pci.Write (PciIo, EfiPciIoWidthUint32, (UINT8) Offset, 1, &gAllOne);\r
+ PciIo->Pci.Read (PciIo, EfiPciIoWidthUint32, (UINT8) Offset, 1, &Value);\r
\r
//\r
// Write back the original value\r
//\r
- PciIoWrite (PciIo, EfiPciIoWidthUint32, (UINT8) Offset, 1, &OriginalValue);\r
+ PciIo->Pci.Write (PciIo, EfiPciIoWidthUint32, (UINT8) Offset, 1, &OriginalValue);\r
\r
//\r
// Restore TPL to its original level\r
}\r
\r
/**\r
- Test whether the device can support attributes \r
- \r
- @param PciIoDevice Pci device instance.\r
- @param Command Command register value.\r
- @param BridgeControl Bridge control value for PPB or P2C.\r
- @param OldCommand Old command register offset.\r
- @param OldBridgeControl Old Bridge control value for PPB or P2C.\r
- \r
- @return EFI_SUCCESS.\r
+ Test whether the device can support given attributes.\r
+\r
+ @param PciIoDevice Pci device instance.\r
+ @param Command Input command register value, and\r
+ returned supported register value.\r
+ @param BridgeControl Inout bridge control value for PPB or P2C, and\r
+ returned supported bridge control value.\r
+ @param OldCommand Returned and stored old command register offset.\r
+ @param OldBridgeControl Returned and stored old Bridge control value for PPB or P2C.\r
+\r
**/\r
-EFI_STATUS\r
+VOID\r
PciTestSupportedAttribute (\r
- IN PCI_IO_DEVICE *PciIoDevice,\r
- IN UINT16 *Command,\r
- IN UINT16 *BridgeControl,\r
- IN UINT16 *OldCommand,\r
- IN UINT16 *OldBridgeControl\r
+ IN PCI_IO_DEVICE *PciIoDevice,\r
+ IN OUT UINT16 *Command,\r
+ IN OUT UINT16 *BridgeControl,\r
+ OUT UINT16 *OldCommand,\r
+ OUT UINT16 *OldBridgeControl\r
)\r
{\r
EFI_TPL OldTpl;\r
//\r
// Preserve the original value\r
//\r
- PciReadCommandRegister (PciIoDevice, OldCommand);\r
+ PCI_READ_COMMAND_REGISTER (PciIoDevice, OldCommand);\r
\r
//\r
// Raise TPL to high level to disable timer interrupt while the BAR is probed\r
//\r
OldTpl = gBS->RaiseTPL (TPL_HIGH_LEVEL);\r
\r
- PciSetCommandRegister (PciIoDevice, *Command);\r
- PciReadCommandRegister (PciIoDevice, Command);\r
+ PCI_SET_COMMAND_REGISTER (PciIoDevice, *Command);\r
+ PCI_READ_COMMAND_REGISTER (PciIoDevice, Command);\r
\r
//\r
// Write back the original value\r
//\r
- PciSetCommandRegister (PciIoDevice, *OldCommand);\r
+ PCI_SET_COMMAND_REGISTER (PciIoDevice, *OldCommand);\r
\r
//\r
// Restore TPL to its original level\r
//\r
// Preserve the original value\r
//\r
- PciReadBridgeControlRegister (PciIoDevice, OldBridgeControl);\r
+ PCI_READ_BRIDGE_CONTROL_REGISTER (PciIoDevice, OldBridgeControl);\r
\r
//\r
// Raise TPL to high level to disable timer interrupt while the BAR is probed\r
//\r
OldTpl = gBS->RaiseTPL (TPL_HIGH_LEVEL);\r
\r
- PciSetBridgeControlRegister (PciIoDevice, *BridgeControl);\r
- PciReadBridgeControlRegister (PciIoDevice, BridgeControl);\r
+ PCI_SET_BRIDGE_CONTROL_REGISTER (PciIoDevice, *BridgeControl);\r
+ PCI_READ_BRIDGE_CONTROL_REGISTER (PciIoDevice, BridgeControl);\r
\r
//\r
// Write back the original value\r
//\r
- PciSetBridgeControlRegister (PciIoDevice, *OldBridgeControl);\r
+ PCI_SET_BRIDGE_CONTROL_REGISTER (PciIoDevice, *OldBridgeControl);\r
\r
//\r
// Restore TPL to its original level\r
*OldBridgeControl = 0;\r
*BridgeControl = 0;\r
}\r
-\r
- return EFI_SUCCESS;\r
}\r
\r
/**\r
- Set the supported or current attributes of a PCI device\r
- \r
- @param PciIoDevice - Structure pointer for PCI device.\r
- @param Command - Command register value.\r
- @param BridgeControl - Bridge control value for PPB or P2C.\r
- @param Option - Make a choice of EFI_SET_SUPPORTS or EFI_SET_ATTRIBUTES.\r
- \r
+ Set the supported or current attributes of a PCI device.\r
+\r
+ @param PciIoDevice Structure pointer for PCI device.\r
+ @param Command Command register value.\r
+ @param BridgeControl Bridge control value for PPB or P2C.\r
+ @param Option Make a choice of EFI_SET_SUPPORTS or EFI_SET_ATTRIBUTES.\r
+\r
**/\r
-EFI_STATUS\r
+VOID\r
PciSetDeviceAttribute (\r
IN PCI_IO_DEVICE *PciIoDevice,\r
IN UINT16 Command,\r
} else {\r
PciIoDevice->Attributes = Attributes;\r
}\r
-\r
- return EFI_SUCCESS;\r
}\r
\r
/**\r
Determine if the device can support Fast Back to Back attribute.\r
- \r
+\r
@param PciIoDevice Pci device instance.\r
@param StatusIndex Status register value.\r
+\r
+ @retval EFI_SUCCESS This device support Fast Back to Back attribute.\r
+ @retval EFI_UNSUPPORTED This device doesn't support Fast Back to Back attribute.\r
+\r
**/\r
EFI_STATUS\r
GetFastBackToBackSupport (\r
// Read the status register\r
//\r
PciIo = &PciIoDevice->PciIo;\r
- Status = PciIoRead (PciIo, EfiPciIoWidthUint16, StatusIndex, 1, &StatusRegister);\r
+ Status = PciIo->Pci.Read (PciIo, EfiPciIoWidthUint16, StatusIndex, 1, &StatusRegister);\r
if (EFI_ERROR (Status)) {\r
return EFI_UNSUPPORTED;\r
}\r
} else {\r
return EFI_UNSUPPORTED;\r
}\r
-\r
}\r
\r
/**\r
It can only be used after the first full Option ROM process.\r
\r
@param PciIoDevice Pci device instance.\r
- \r
- @retval EFI_SUCCESS Success Operation.\r
+\r
**/\r
-EFI_STATUS\r
+VOID\r
ProcessOptionRomLight (\r
IN PCI_IO_DEVICE *PciIoDevice\r
)\r
\r
CurrentLink = CurrentLink->ForwardLink;\r
}\r
-\r
- return EFI_SUCCESS;\r
}\r
\r
/**\r
- Determine the related attributes of all devices under a Root Bridge\r
- \r
- @param PciIoDevice PCI device instance.\r
- \r
+ Determine the related attributes of all devices under a Root Bridge.\r
+\r
+ @param PciIoDevice PCI device instance.\r
+\r
**/\r
EFI_STATUS\r
DetermineDeviceAttribute (\r
UINT16 OldCommand;\r
UINT16 OldBridgeControl;\r
BOOLEAN FastB2BSupport;\r
-\r
- /*\r
- UINT8 IdePI;\r
- EFI_PCI_IO_PROTOCOL *PciIo;\r
- */\r
PCI_IO_DEVICE *Temp;\r
LIST_ENTRY *CurrentLink;\r
EFI_STATUS Status;\r
//\r
// Enable other supported attributes but not defined in PCI_IO_PROTOCOL\r
//\r
- PciEnableCommandRegister (PciIoDevice, EFI_PCI_COMMAND_MEMORY_WRITE_AND_INVALIDATE);\r
-\r
- //\r
- // Enable IDE native mode\r
- //\r
- /*\r
- if (IS_PCI_IDE(&PciIoDevice->Pci)) {\r
-\r
- PciIo = &PciIoDevice->PciIo;\r
-\r
- PciIoRead (\r
- PciIo,\r
- EfiPciIoWidthUint8,\r
- 0x09,\r
- 1,\r
- &IdePI\r
- );\r
-\r
- //\r
- // Set native mode if it can be supported\r
- //\r
- IdePI |= (((IdePI & 0x0F) >> 1) & 0x05);\r
-\r
- PciIoWrite (\r
- PciIo,\r
- EfiPciIoWidthUint8,\r
- 0x09,\r
- 1,\r
- &IdePI\r
- );\r
-\r
- }\r
- */\r
+ PCI_ENABLE_COMMAND_REGISTER (PciIoDevice, EFI_PCI_COMMAND_MEMORY_WRITE_AND_INVALIDATE);\r
}\r
\r
FastB2BSupport = TRUE;\r
\r
if (EFI_ERROR (Status) || (!FastB2BSupport)) {\r
FastB2BSupport = FALSE;\r
- PciDisableBridgeControlRegister (PciIoDevice, EFI_PCI_BRIDGE_CONTROL_FAST_BACK_TO_BACK);\r
+ PCI_DISABLE_BRIDGE_CONTROL_REGISTER (PciIoDevice, EFI_PCI_BRIDGE_CONTROL_FAST_BACK_TO_BACK);\r
} else {\r
- PciEnableBridgeControlRegister (PciIoDevice, EFI_PCI_BRIDGE_CONTROL_FAST_BACK_TO_BACK);\r
+ PCI_ENABLE_BRIDGE_CONTROL_REGISTER (PciIoDevice, EFI_PCI_BRIDGE_CONTROL_FAST_BACK_TO_BACK);\r
}\r
}\r
\r
while (CurrentLink != NULL && CurrentLink != &PciIoDevice->ChildList) {\r
Temp = PCI_IO_DEVICE_FROM_LINK (CurrentLink);\r
if (FastB2BSupport) {\r
- PciEnableCommandRegister (Temp, EFI_PCI_COMMAND_FAST_BACK_TO_BACK);\r
+ PCI_ENABLE_COMMAND_REGISTER (Temp, EFI_PCI_COMMAND_FAST_BACK_TO_BACK);\r
} else {\r
- PciDisableCommandRegister (Temp, EFI_PCI_COMMAND_FAST_BACK_TO_BACK);\r
+ PCI_DISABLE_COMMAND_REGISTER (Temp, EFI_PCI_COMMAND_FAST_BACK_TO_BACK);\r
}\r
\r
CurrentLink = CurrentLink->ForwardLink;\r
}\r
\r
/**\r
- This routine is used to update the bar information for those incompatible PCI device\r
- \r
- @param PciIoDevice Pci device instance.\r
- @return EFI_UNSUPPORTED failed to update Pci Info.\r
+ This routine is used to update the bar information for those incompatible PCI device.\r
+\r
+ @param PciIoDevice Input Pci device instance. Output Pci device instance with updated\r
+ Bar information.\r
+\r
+ @retval EFI_SUCCESS Successfully updated bar information.\r
+ @retval EFI_UNSUPPORTED Given PCI device doesn't belong to incompatible PCI device list.\r
+\r
**/\r
EFI_STATUS\r
UpdatePciInfo (\r
- IN PCI_IO_DEVICE *PciIoDevice\r
+ IN OUT PCI_IO_DEVICE *PciIoDevice\r
)\r
{\r
EFI_STATUS Status;\r
UINTN BarIndex;\r
UINTN BarEndIndex;\r
BOOLEAN SetFlag;\r
- EFI_PCI_DEVICE_INFO PciDeviceInfo;\r
VOID *Configuration;\r
EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Ptr;\r
\r
// If it is , then get its special requirement in the ACPI table\r
//\r
Status = gEfiIncompatiblePciDeviceSupport->CheckDevice (\r
- gEfiIncompatiblePciDeviceSupport,\r
- PciIoDevice->Pci.Hdr.VendorId,\r
- PciIoDevice->Pci.Hdr.DeviceId,\r
- PciIoDevice->Pci.Hdr.RevisionID,\r
- PciIoDevice->Pci.Device.SubsystemVendorID,\r
- PciIoDevice->Pci.Device.SubsystemID,\r
- &Configuration\r
- );\r
-\r
- }\r
+ gEfiIncompatiblePciDeviceSupport,\r
+ PciIoDevice->Pci.Hdr.VendorId,\r
+ PciIoDevice->Pci.Hdr.DeviceId,\r
+ PciIoDevice->Pci.Hdr.RevisionID,\r
+ PciIoDevice->Pci.Device.SubsystemVendorID,\r
+ PciIoDevice->Pci.Device.SubsystemID,\r
+ &Configuration\r
+ );\r
\r
- if (EFI_ERROR (Status)) {\r
- //\r
- // Check whether the device belongs to incompatible devices from library or not\r
- // If it is , then get its special requirement in the ACPI table\r
- //\r
- if (PcdGet8 (PcdPciIncompatibleDeviceSupportMask) & PCI_INCOMPATIBLE_ACPI_RESOURCE_SUPPORT) {\r
- PciDeviceInfo.VendorID = PciIoDevice->Pci.Hdr.VendorId;\r
- PciDeviceInfo.DeviceID = PciIoDevice->Pci.Hdr.DeviceId;\r
- PciDeviceInfo.RevisionID = PciIoDevice->Pci.Hdr.RevisionID;\r
- PciDeviceInfo.SubsystemVendorID = PciIoDevice->Pci.Device.SubsystemVendorID;\r
- PciDeviceInfo.SubsystemID = PciIoDevice->Pci.Device.SubsystemID;\r
-\r
- Status = PciResourceUpdateCheck (&PciDeviceInfo, &Configuration);\r
- }\r
}\r
\r
- if (EFI_ERROR (Status)) {\r
+ if (EFI_ERROR (Status) || Configuration == NULL ) {\r
return EFI_UNSUPPORTED;\r
}\r
\r
Ptr++;\r
}\r
\r
- gBS->FreePool (Configuration);\r
- return Status;\r
+ FreePool (Configuration);\r
\r
+ return EFI_SUCCESS;\r
}\r
\r
/**\r
- This routine will update the alignment with the new alignment\r
- \r
- @param Alignment old alignment.\r
- @param NewAlignment new alignment.\r
- \r
+ This routine will update the alignment with the new alignment.\r
+\r
+ @param Alignment Input Old alignment. Output updated alignment.\r
+ @param NewAlignment New alignment.\r
+\r
**/\r
VOID\r
SetNewAlign (\r
- IN UINT64 *Alignment,\r
- IN UINT64 NewAlignment\r
+ IN OUT UINT64 *Alignment,\r
+ IN UINT64 NewAlignment\r
)\r
{\r
UINT64 OldAlignment;\r
}\r
\r
/**\r
- Parse PCI bar bit.\r
- \r
+ Parse PCI bar information and fill them into PCI device instance.\r
+\r
@param PciIoDevice Pci device instance.\r
- @param Offset bar offset.\r
- @param BarIndex bar index.\r
- \r
- @return next bar offset.\r
+ @param Offset Bar offset.\r
+ @param BarIndex Bar index.\r
+\r
+ @return Next bar offset.\r
+\r
**/\r
UINTN\r
PciParseBar (\r
Value = 0;\r
\r
Status = BarExisted (\r
- PciIoDevice,\r
- Offset,\r
- &Value,\r
- &OriginalValue\r
- );\r
+ PciIoDevice,\r
+ Offset,\r
+ &Value,\r
+ &OriginalValue\r
+ );\r
\r
if (EFI_ERROR (Status)) {\r
PciIoDevice->PciBar[BarIndex].BaseAddress = 0;\r
Offset += 4;\r
\r
Status = BarExisted (\r
- PciIoDevice,\r
- Offset,\r
- &Value,\r
- &OriginalValue\r
- );\r
+ PciIoDevice,\r
+ Offset,\r
+ &Value,\r
+ &OriginalValue\r
+ );\r
\r
if (EFI_ERROR (Status)) {\r
return Offset + 4;\r
\r
/**\r
This routine is used to initialize the bar of a PCI device.\r
- It can be called typically when a device is going to be rejected.\r
\r
@param PciIoDevice Pci device instance.\r
+\r
+ @note It can be called typically when a device is going to be rejected.\r
+\r
**/\r
-EFI_STATUS\r
+VOID\r
InitializePciDevice (\r
- IN PCI_IO_DEVICE *PciIoDevice\r
+ IN PCI_IO_DEVICE *PciIoDevice\r
)\r
{\r
EFI_PCI_IO_PROTOCOL *PciIo;\r
// has not been alloacted\r
//\r
for (Offset = 0x10; Offset <= 0x24; Offset += sizeof (UINT32)) {\r
- PciIoWrite (PciIo, EfiPciIoWidthUint32, Offset, 1, &gAllOne);\r
+ PciIo->Pci.Write (PciIo, EfiPciIoWidthUint32, Offset, 1, &gAllOne);\r
}\r
-\r
- return EFI_SUCCESS;\r
}\r
\r
/**\r
- Init PPB for bridge device\r
- \r
- @param PciIoDevice Pci device instance.\r
+ This routine is used to initialize the bar of a PCI-PCI Bridge device.\r
+\r
+ @param PciIoDevice PCI-PCI bridge device instance.\r
+\r
**/\r
-EFI_STATUS\r
+VOID\r
InitializePpb (\r
- IN PCI_IO_DEVICE *PciIoDevice\r
+ IN PCI_IO_DEVICE *PciIoDevice\r
)\r
{\r
EFI_PCI_IO_PROTOCOL *PciIo;\r
// Io32, pMem32, pMem64 to quiescent state\r
// Resource base all ones, Resource limit all zeros\r
//\r
- PciIoWrite (PciIo, EfiPciIoWidthUint8, 0x1C, 1, &gAllOne);\r
- PciIoWrite (PciIo, EfiPciIoWidthUint8, 0x1D, 1, &gAllZero);\r
+ PciIo->Pci.Write (PciIo, EfiPciIoWidthUint8, 0x1C, 1, &gAllOne);\r
+ PciIo->Pci.Write (PciIo, EfiPciIoWidthUint8, 0x1D, 1, &gAllZero);\r
\r
- PciIoWrite (PciIo, EfiPciIoWidthUint16, 0x20, 1, &gAllOne);\r
- PciIoWrite (PciIo, EfiPciIoWidthUint16, 0x22, 1, &gAllZero);\r
+ PciIo->Pci.Write (PciIo, EfiPciIoWidthUint16, 0x20, 1, &gAllOne);\r
+ PciIo->Pci.Write (PciIo, EfiPciIoWidthUint16, 0x22, 1, &gAllZero);\r
\r
- PciIoWrite (PciIo, EfiPciIoWidthUint16, 0x24, 1, &gAllOne);\r
- PciIoWrite (PciIo, EfiPciIoWidthUint16, 0x26, 1, &gAllZero);\r
+ PciIo->Pci.Write (PciIo, EfiPciIoWidthUint16, 0x24, 1, &gAllOne);\r
+ PciIo->Pci.Write (PciIo, EfiPciIoWidthUint16, 0x26, 1, &gAllZero);\r
\r
- PciIoWrite (PciIo, EfiPciIoWidthUint32, 0x28, 1, &gAllOne);\r
- PciIoWrite (PciIo, EfiPciIoWidthUint32, 0x2C, 1, &gAllZero);\r
+ PciIo->Pci.Write (PciIo, EfiPciIoWidthUint32, 0x28, 1, &gAllOne);\r
+ PciIo->Pci.Write (PciIo, EfiPciIoWidthUint32, 0x2C, 1, &gAllZero);\r
\r
//\r
- // don't support use io32 as for now\r
+ // Don't support use io32 as for now\r
//\r
- PciIoWrite (PciIo, EfiPciIoWidthUint16, 0x30, 1, &gAllOne);\r
- PciIoWrite (PciIo, EfiPciIoWidthUint16, 0x32, 1, &gAllZero);\r
+ PciIo->Pci.Write (PciIo, EfiPciIoWidthUint16, 0x30, 1, &gAllOne);\r
+ PciIo->Pci.Write (PciIo, EfiPciIoWidthUint16, 0x32, 1, &gAllZero);\r
\r
//\r
// Force Interrupt line to zero for cards that come up randomly\r
//\r
- PciIoWrite (PciIo, EfiPciIoWidthUint8, 0x3C, 1, &gAllZero);\r
-\r
- return EFI_SUCCESS;\r
+ PciIo->Pci.Write (PciIo, EfiPciIoWidthUint8, 0x3C, 1, &gAllZero);\r
}\r
\r
/**\r
- Init private data for Hotplug bridge device\r
- \r
- @param PciIoDevice hotplug bridge device.\r
+ This routine is used to initialize the bar of a PCI Card Bridge device.\r
+\r
+ @param PciIoDevice PCI Card bridge device.\r
+\r
**/\r
-EFI_STATUS\r
+VOID\r
InitializeP2C (\r
- IN PCI_IO_DEVICE *PciIoDevice\r
+ IN PCI_IO_DEVICE *PciIoDevice\r
)\r
{\r
EFI_PCI_IO_PROTOCOL *PciIo;\r
// Io32, pMem32, pMem64 to quiescent state(\r
// Resource base all ones, Resource limit all zeros\r
//\r
- PciIoWrite (PciIo, EfiPciIoWidthUint32, 0x1c, 1, &gAllOne);\r
- PciIoWrite (PciIo, EfiPciIoWidthUint32, 0x20, 1, &gAllZero);\r
+ PciIo->Pci.Write (PciIo, EfiPciIoWidthUint32, 0x1c, 1, &gAllOne);\r
+ PciIo->Pci.Write (PciIo, EfiPciIoWidthUint32, 0x20, 1, &gAllZero);\r
\r
- PciIoWrite (PciIo, EfiPciIoWidthUint32, 0x24, 1, &gAllOne);\r
- PciIoWrite (PciIo, EfiPciIoWidthUint32, 0x28, 1, &gAllZero);\r
+ PciIo->Pci.Write (PciIo, EfiPciIoWidthUint32, 0x24, 1, &gAllOne);\r
+ PciIo->Pci.Write (PciIo, EfiPciIoWidthUint32, 0x28, 1, &gAllZero);\r
\r
- PciIoWrite (PciIo, EfiPciIoWidthUint32, 0x2c, 1, &gAllOne);\r
- PciIoWrite (PciIo, EfiPciIoWidthUint32, 0x30, 1, &gAllZero);\r
+ PciIo->Pci.Write (PciIo, EfiPciIoWidthUint32, 0x2c, 1, &gAllOne);\r
+ PciIo->Pci.Write (PciIo, EfiPciIoWidthUint32, 0x30, 1, &gAllZero);\r
\r
- PciIoWrite (PciIo, EfiPciIoWidthUint32, 0x34, 1, &gAllOne);\r
- PciIoWrite (PciIo, EfiPciIoWidthUint32, 0x38, 1, &gAllZero);\r
+ PciIo->Pci.Write (PciIo, EfiPciIoWidthUint32, 0x34, 1, &gAllOne);\r
+ PciIo->Pci.Write (PciIo, EfiPciIoWidthUint32, 0x38, 1, &gAllZero);\r
\r
//\r
// Force Interrupt line to zero for cards that come up randomly\r
//\r
- PciIoWrite (PciIo, EfiPciIoWidthUint8, 0x3C, 1, &gAllZero);\r
- return EFI_SUCCESS;\r
+ PciIo->Pci.Write (PciIo, EfiPciIoWidthUint8, 0x3C, 1, &gAllZero);\r
}\r
\r
/**\r
Create and initiliaze general PCI I/O device instance for\r
PCI device/bridge device/hotplug bridge device.\r
- \r
+\r
@param PciRootBridgeIo Pointer to instance of EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.\r
- @param Pci Pci bar block.\r
- @param Bus device Bus NO.\r
- @param Device device device NO.\r
- @param Func device func NO.\r
- \r
- @return instance of PCI device.\r
+ @param Pci Input Pci information block.\r
+ @param Bus Device Bus NO.\r
+ @param Device Device device NO.\r
+ @param Func Device func NO.\r
+\r
+ @return Instance of PCI device. NULL means no instance created.\r
+\r
**/\r
PCI_IO_DEVICE *\r
CreatePciIoDevice (\r
IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *PciRootBridgeIo,\r
IN PCI_TYPE00 *Pci,\r
- UINT8 Bus,\r
- UINT8 Device,\r
- UINT8 Func\r
+ IN UINT8 Bus,\r
+ IN UINT8 Device,\r
+ IN UINT8 Func\r
)\r
{\r
-\r
- EFI_STATUS Status;\r
PCI_IO_DEVICE *PciIoDevice;\r
\r
- PciIoDevice = NULL;\r
-\r
- Status = gBS->AllocatePool (\r
- EfiBootServicesData,\r
- sizeof (PCI_IO_DEVICE),\r
- (VOID **) &PciIoDevice\r
- );\r
-\r
- if (EFI_ERROR (Status)) {\r
+ PciIoDevice = AllocateZeroPool (sizeof (PCI_IO_DEVICE));\r
+ if (PciIoDevice == NULL) {\r
return NULL;\r
}\r
\r
- ZeroMem (PciIoDevice, sizeof (PCI_IO_DEVICE));\r
-\r
PciIoDevice->Signature = PCI_IO_DEVICE_SIGNATURE;\r
PciIoDevice->Handle = NULL;\r
PciIoDevice->PciRootBridgeIo = PciRootBridgeIo;\r
PciIoDevice->DeviceNumber = Device;\r
PciIoDevice->FunctionNumber = Func;\r
PciIoDevice->Decodes = 0;\r
+\r
if (gFullEnumeration) {\r
PciIoDevice->Allocated = FALSE;\r
} else {\r
//\r
// Initialize the PCI I/O instance structure\r
//\r
-\r
- Status = InitializePciIoInstance (PciIoDevice);\r
- Status = InitializePciDriverOverrideInstance (PciIoDevice);\r
-\r
- if (EFI_ERROR (Status)) {\r
- gBS->FreePool (PciIoDevice);\r
- return NULL;\r
- }\r
+ InitializePciIoInstance (PciIoDevice);\r
+ InitializePciDriverOverrideInstance (PciIoDevice);\r
+ InitializePciLoadFile2 (PciIoDevice);\r
\r
//\r
// Initialize the reserved resource list\r
\r
/**\r
This routine is used to enumerate entire pci bus system\r
- in a given platform\r
+ in a given platform.\r
+\r
It is only called on the second start on the same Root Bridge.\r
\r
- @param Controller Parent bridge handler.\r
- \r
- @return status of operation.\r
+ @param Controller Parent bridge handler.\r
+\r
+ @retval EFI_SUCCESS PCI enumeration finished successfully.\r
+ @retval other Some error occurred when enumerating the pci bus system.\r
+\r
**/\r
EFI_STATUS\r
PciEnumeratorLight (\r
}\r
\r
//\r
- // Record the root bridge io protocol\r
+ // Record the root bridgeio protocol\r
//\r
RootBridgeDev->PciRootBridgeIo = PciRootBridgeIo;\r
\r
Status = PciPciDeviceInfoCollector (\r
- RootBridgeDev,\r
- (UINT8) MinBus\r
- );\r
+ RootBridgeDev,\r
+ (UINT8) MinBus\r
+ );\r
\r
if (!EFI_ERROR (Status)) {\r
\r
}\r
\r
/**\r
- Get bus range.\r
- \r
+ Get bus range from PCI resource descriptor list.\r
+\r
@param Descriptors A pointer to the address space descriptor.\r
- @param MinBus The min bus.\r
- @param MaxBus The max bus.\r
- @param BusRange The bus range.\r
- \r
- @retval EFI_SUCCESS Success operation.\r
- @retval EFI_NOT_FOUND can not find the specific bus.\r
+ @param MinBus The min bus returned.\r
+ @param MaxBus The max bus returned.\r
+ @param BusRange The bus range returned.\r
+\r
+ @retval EFI_SUCCESS Successfully got bus range.\r
+ @retval EFI_NOT_FOUND Can not find the specific bus.\r
+\r
**/\r
EFI_STATUS\r
PciGetBusRange (\r
OUT UINT16 *BusRange\r
)\r
{\r
-\r
while ((*Descriptors)->Desc != ACPI_END_TAG_DESCRIPTOR) {\r
if ((*Descriptors)->ResType == ACPI_ADDRESS_SPACE_TYPE_BUS) {\r
if (MinBus != NULL) {\r
@param RootBridgeDev Pci device instance.\r
\r
@retval EFI_SUCCESS This device started.\r
- \r
+ @retval other Failed to get PCI Root Bridge I/O protocol.\r
+\r
**/\r
EFI_STATUS\r
StartManagingRootBridge (\r
//\r
// Get the root bridge handle\r
//\r
- RootBridgeHandle = RootBridgeDev->Handle;\r
- PciRootBridgeIo = NULL;\r
+ RootBridgeHandle = RootBridgeDev->Handle;\r
+ PciRootBridgeIo = NULL;\r
\r
//\r
// Get the pci root bridge io protocol\r
}\r
\r
/**\r
- This routine can be used to check whether a PCI device should be rejected when light enumeration\r
+ This routine can be used to check whether a PCI device should be rejected when light enumeration.\r
\r
@param PciIoDevice Pci device instance.\r
\r
@retval TRUE This device should be rejected.\r
@retval FALSE This device shouldn't be rejected.\r
- \r
+\r
**/\r
BOOLEAN\r
IsPciDeviceRejected (\r
//\r
// IO Bar\r
//\r
-\r
Mask = 0xFFFFFFFC;\r
TestValue = TestValue & Mask;\r
if ((TestValue != 0) && (TestValue == (OldValue & Mask))) {\r
//\r
// Mem Bar\r
//\r
-\r
Mask = 0xFFFFFFF0;\r
TestValue = TestValue & Mask;\r
\r
//\r
// Test its high 32-Bit BAR\r
//\r
-\r
Status = BarExisted (PciIoDevice, BarOffset, &TestValue, &OldValue);\r
if (TestValue == OldValue) {\r
return TRUE;\r
}\r
\r
/**\r
- Reset and all bus number from specific bridge.\r
- \r
+ Reset all bus number from specific bridge.\r
+\r
@param Bridge Parent specific bridge.\r
- @param StartBusNumber start bus number.\r
+ @param StartBusNumber Start bus number.\r
+\r
**/\r
-EFI_STATUS\r
+VOID\r
ResetAllPpbBusNumber (\r
IN PCI_IO_DEVICE *Bridge,\r
IN UINT8 StartBusNumber\r
// Check to see whether a pci device is present\r
//\r
Status = PciDevicePresent (\r
- PciRootBridgeIo,\r
- &Pci,\r
- StartBusNumber,\r
- Device,\r
- Func\r
- );\r
+ PciRootBridgeIo,\r
+ &Pci,\r
+ StartBusNumber,\r
+ Device,\r
+ Func\r
+ );\r
\r
if (!EFI_ERROR (Status) && (IS_PCI_BRIDGE (&Pci))) {\r
\r
Register = 0;\r
Address = EFI_PCI_ADDRESS (StartBusNumber, Device, Func, 0x18);\r
- Status = PciRootBridgeIoRead (\r
- PciRootBridgeIo,\r
- &Pci,\r
- EfiPciWidthUint32,\r
- Address,\r
- 1,\r
- &Register\r
- );\r
+ Status = PciRootBridgeIo->Pci.Read (\r
+ PciRootBridgeIo,\r
+ EfiPciWidthUint32,\r
+ Address,\r
+ 1,\r
+ &Register\r
+ );\r
SecondaryBus = (UINT8)(Register >> 8);\r
\r
if (SecondaryBus != 0) {\r
// Reset register 18h, 19h, 1Ah on PCI Bridge\r
//\r
Register &= 0xFF000000;\r
- Status = PciRootBridgeIoWrite (\r
+ Status = PciRootBridgeIo->Pci.Write (\r
PciRootBridgeIo,\r
- &Pci,\r
EfiPciWidthUint32,\r
Address,\r
1,\r
}\r
}\r
}\r
-\r
- return EFI_SUCCESS;\r
}\r
\r
projects / mirror_edk2.git / blobdiff