Take the highest horizontal resolution as highest video resolution.

[mirror_edk2.git] / IntelFrameworkModulePkg / Csm / LegacyBiosDxe / LegacyBiosInterface.h

diff --git a/IntelFrameworkModulePkg/Csm/LegacyBiosDxe/LegacyBiosInterface.h b/IntelFrameworkModulePkg/Csm/LegacyBiosDxe/LegacyBiosInterface.h
index 15b3b7048cf99548dcc85a8a617f65b23cec20db..a63a7257def2685594c54274dc9474a653e2bf8e 100644 (file)
--- a/IntelFrameworkModulePkg/Csm/LegacyBiosDxe/LegacyBiosInterface.h
+++ b/IntelFrameworkModulePkg/Csm/LegacyBiosDxe/LegacyBiosInterface.h
@@ -1,6 +1,6 @@
 /** @file\r
 \r
-Copyright (c) 2006 - 2011, Intel Corporation. All rights reserved.<BR>\r
+Copyright (c) 2006 - 2012, Intel Corporation. All rights reserved.<BR>\r
 \r
 This program and the accompanying materials\r
 are licensed and made available under the terms and conditions\r
@@ -18,17 +18,20 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
 \r
 \r
 #include <FrameworkDxe.h>\r
+#include <IndustryStandard/Pci.h>\r
 \r
 #include <Guid/SmBios.h>\r
 #include <Guid/Acpi.h>\r
 #include <Guid/DxeServices.h>\r
 #include <Guid/LegacyBios.h>\r
 #include <Guid/StatusCodeDataTypeId.h>\r
+#include <Guid/ImageAuthentication.h>\r
 \r
 #include <Protocol/BlockIo.h>\r
 #include <Protocol/LoadedImage.h>\r
 #include <Protocol/PciIo.h>\r
 #include <Protocol/Cpu.h>\r
+#include <Protocol/Timer.h>\r
 #include <Protocol/IsaIo.h>\r
 #include <Protocol/LegacyRegion2.h>\r
 #include <Protocol/SimpleTextIn.h>\r
@@ -92,6 +95,14 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
 #define PROTECTED_MODE_BASE_VECTOR_MASTER  0x68\r
 #define PROTECTED_MODE_BASE_VECTOR_SLAVE   0x70\r
 \r
+//\r
+// When we call CSM16 functions, some CSM16 use es:[offset + 0xabcd] to get data passed from CSM32, \r
+// offset + 0xabcd could overflow which exceeds 0xFFFF which is invalid in real mode. \r
+// So this will keep offset as small as possible to avoid offset overflow in real mode. \r
+//\r
+#define NORMALIZE_EFI_SEGMENT(_Adr)      (UINT16) (((UINTN) (_Adr)) >> 4)\r
+#define NORMALIZE_EFI_OFFSET(_Adr)       (UINT16) (((UINT16) ((UINTN) (_Adr))) & 0xf)\r
+\r
 //\r
 // Trace defines\r
 //\r
@@ -122,6 +133,10 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
 #define LEGACY_PCI_TRACE_00E LEGACY_PCI_TRACE + 0x0E\r
 #define LEGACY_PCI_TRACE_00F LEGACY_PCI_TRACE + 0x0F\r
 \r
+#define BDA_VIDEO_MODE      0x49\r
+\r
+#define IDE_PI_REGISTER_PNE     BIT0\r
+#define IDE_PI_REGISTER_SNE     BIT2\r
 \r
 typedef struct {\r
   UINTN   PciSegment;\r
@@ -157,11 +172,6 @@ typedef struct {
 \r
 #endif\r
 \r
-//\r
-// Miscellaneous numbers\r
-//\r
-#define PMM_MEMORY_SIZE         0x400000  // 4 MB\r
-\r
 #pragma pack(1)\r
 \r
 //\r
@@ -493,8 +503,6 @@ extern BBS_TABLE           *mBbsTable;
 \r
 extern EFI_GENERIC_MEMORY_TEST_PROTOCOL *gGenMemoryTest;\r
 \r
-extern UINTN               mEndOpromShadowAddress;\r
-\r
 #define PORT_70 0x70\r
 #define PORT_71 0x71\r
 \r
@@ -517,6 +525,18 @@ extern UINTN               mEndOpromShadowAddress;
 #define CMOS_31     0x31  ///< CMOS 0x18\r
 #define CMOS_32     0x32  ///< Century byte\r
 \r
+//\r
+// 8254 Timer registers\r
+//\r
+#define TIMER0_COUNT_PORT                         0x40\r
+#define TIMER1_COUNT_PORT                         0x41\r
+#define TIMER2_COUNT_PORT                         0x42\r
+#define TIMER_CONTROL_PORT                        0x43\r
+\r
+//\r
+// Timer 0, Read/Write LSB then MSB, Square wave output, binary count use.\r
+//\r
+#define TIMER0_CONTROL_WORD         0x36      \r
 \r
 #define LEGACY_BIOS_INSTANCE_SIGNATURE  SIGNATURE_32 ('L', 'B', 'I', 'T')\r
 typedef struct {\r
@@ -532,6 +552,12 @@ typedef struct {
   //\r
   EFI_CPU_ARCH_PROTOCOL             *Cpu;\r
 \r
+  //\r
+  // Timer Architectural Protocol \r
+  //\r
+  EFI_TIMER_ARCH_PROTOCOL           *Timer;\r
+  BOOLEAN                           TimerUses8254; \r
+  \r
   //\r
   // Protocol to Lock and Unlock 0xc0000 - 0xfffff\r
   //\r
@@ -543,7 +569,7 @@ typedef struct {
   // Interrupt control for thunk and PCI IRQ\r
   //\r
   EFI_LEGACY_8259_PROTOCOL          *Legacy8259;\r
-\r
+  \r
   //\r
   // PCI Interrupt PIRQ control\r
   //\r