This is an implementation of the ACPI S3 Save protocol. This is defined in\r
S3 boot path specification 0.9.\r
\r
-Copyright (c) 2006 - 2014, Intel Corporation. All rights reserved.<BR>\r
+Copyright (c) 2006 - 2015, Intel Corporation. All rights reserved.<BR>\r
\r
This program and the accompanying materials\r
are licensed and made available under the terms and conditions\r
\r
#include "AcpiS3Save.h"\r
\r
+//\r
+// 8 extra pages for PF handler.\r
+//\r
+#define EXTRA_PAGE_TABLE_PAGES 8\r
+\r
/**\r
Hook point for AcpiVariableThunkPlatform for InstallAcpiS3Save.\r
**/\r
}\r
\r
/**\r
- Allocates and fills in the Page Directory and Page Table Entries to\r
- establish a 1:1 Virtual to Physical mapping.\r
+ The function will check if long mode waking vector is supported.\r
+\r
+ @param[in] Facs Pointer to FACS table.\r
+\r
+ @retval TRUE Long mode waking vector is supported.\r
+ @retval FALSE Long mode waking vector is not supported.\r
+\r
+**/\r
+BOOLEAN\r
+IsLongModeWakingVectorSupport (\r
+ IN EFI_ACPI_4_0_FIRMWARE_ACPI_CONTROL_STRUCTURE *Facs\r
+ )\r
+{\r
+ if ((Facs == NULL) ||\r
+ (Facs->Signature != EFI_ACPI_4_0_FIRMWARE_ACPI_CONTROL_STRUCTURE_SIGNATURE) ) {\r
+ //\r
+ // Something wrong with FACS.\r
+ //\r
+ return FALSE;\r
+ }\r
+ if (Facs->XFirmwareWakingVector != 0) {\r
+ if ((Facs->Version == EFI_ACPI_4_0_FIRMWARE_ACPI_CONTROL_STRUCTURE_VERSION) &&\r
+ ((Facs->Flags & EFI_ACPI_4_0_64BIT_WAKE_SUPPORTED_F) != 0)) {\r
+ //\r
+ // BIOS supports 64bit waking vector.\r
+ //\r
+ if (FeaturePcdGet (PcdDxeIplSwitchToLongMode)) {\r
+ return TRUE;\r
+ }\r
+ }\r
+ }\r
+ return FALSE;\r
+}\r
+\r
+/**\r
+ Allocates page table buffer.\r
+\r
+ @param[in] LongModeWakingVectorSupport Support long mode waking vector or not.\r
+\r
If BootScriptExector driver will run in 64-bit mode, this function will establish the 1:1 \r
- virtual to physical mapping page table.\r
+ virtual to physical mapping page table when long mode waking vector is supported, otherwise\r
+ create 4G page table when long mode waking vector is not supported and let PF handler to\r
+ handle > 4G request.\r
If BootScriptExector driver will not run in 64-bit mode, this function will do nothing. \r
\r
- @return the 1:1 Virtual to Physical identity mapping page table base address. \r
+ @return Page table base address. \r
\r
**/\r
EFI_PHYSICAL_ADDRESS\r
-S3CreateIdentityMappingPageTables (\r
- VOID\r
+S3AllocatePageTablesBuffer (\r
+ IN BOOLEAN LongModeWakingVectorSupport\r
)\r
{ \r
if (FeaturePcdGet (PcdDxeIplSwitchToLongMode)) {\r
+ UINTN ExtraPageTablePages;\r
UINT32 RegEax;\r
UINT32 RegEdx;\r
UINT8 PhysicalAddressBits;\r
VOID *Hob;\r
BOOLEAN Page1GSupport;\r
\r
- S3NvsPageTableAddress = (EFI_PHYSICAL_ADDRESS) PcdGet64 (PcdIdentifyMappingPageTablePtr);\r
- if (S3NvsPageTableAddress != 0x0) {\r
- return S3NvsPageTableAddress;\r
- } else {\r
- Page1GSupport = FALSE;\r
- if (PcdGetBool(PcdUse1GPageTable)) {\r
- AsmCpuid (0x80000000, &RegEax, NULL, NULL, NULL);\r
- if (RegEax >= 0x80000001) {\r
- AsmCpuid (0x80000001, NULL, NULL, NULL, &RegEdx);\r
- if ((RegEdx & BIT26) != 0) {\r
- Page1GSupport = TRUE;\r
- }\r
+ Page1GSupport = FALSE;\r
+ if (PcdGetBool(PcdUse1GPageTable)) {\r
+ AsmCpuid (0x80000000, &RegEax, NULL, NULL, NULL);\r
+ if (RegEax >= 0x80000001) {\r
+ AsmCpuid (0x80000001, NULL, NULL, NULL, &RegEdx);\r
+ if ((RegEdx & BIT26) != 0) {\r
+ Page1GSupport = TRUE;\r
}\r
}\r
- \r
- //\r
- // Get physical address bits supported.\r
- //\r
- Hob = GetFirstHob (EFI_HOB_TYPE_CPU);\r
- if (Hob != NULL) {\r
- PhysicalAddressBits = ((EFI_HOB_CPU *) Hob)->SizeOfMemorySpace;\r
- } else {\r
- AsmCpuid (0x80000000, &RegEax, NULL, NULL, NULL);\r
- if (RegEax >= 0x80000008) {\r
- AsmCpuid (0x80000008, &RegEax, NULL, NULL, NULL);\r
- PhysicalAddressBits = (UINT8) RegEax;\r
- } else {\r
- PhysicalAddressBits = 36;\r
- }\r
- }\r
- \r
- //\r
- // IA-32e paging translates 48-bit linear addresses to 52-bit physical addresses.\r
- //\r
- ASSERT (PhysicalAddressBits <= 52);\r
- if (PhysicalAddressBits > 48) {\r
- PhysicalAddressBits = 48;\r
- }\r
- \r
- //\r
- // Calculate the table entries needed.\r
- //\r
- if (PhysicalAddressBits <= 39 ) {\r
- NumberOfPml4EntriesNeeded = 1;\r
- NumberOfPdpEntriesNeeded = (UINT32)LShiftU64 (1, (PhysicalAddressBits - 30));\r
- } else {\r
- NumberOfPml4EntriesNeeded = (UINT32)LShiftU64 (1, (PhysicalAddressBits - 39));\r
- NumberOfPdpEntriesNeeded = 512;\r
- }\r
- \r
- //\r
- // We need calculate whole page size then allocate once, because S3 restore page table does not know each page in Nvs.\r
- //\r
- if (!Page1GSupport) {\r
- TotalPageTableSize = (UINTN)(1 + NumberOfPml4EntriesNeeded + NumberOfPml4EntriesNeeded * NumberOfPdpEntriesNeeded);\r
+ }\r
+\r
+ //\r
+ // Get physical address bits supported.\r
+ //\r
+ Hob = GetFirstHob (EFI_HOB_TYPE_CPU);\r
+ if (Hob != NULL) {\r
+ PhysicalAddressBits = ((EFI_HOB_CPU *) Hob)->SizeOfMemorySpace;\r
+ } else {\r
+ AsmCpuid (0x80000000, &RegEax, NULL, NULL, NULL);\r
+ if (RegEax >= 0x80000008) {\r
+ AsmCpuid (0x80000008, &RegEax, NULL, NULL, NULL);\r
+ PhysicalAddressBits = (UINT8) RegEax;\r
} else {\r
- TotalPageTableSize = (UINTN)(1 + NumberOfPml4EntriesNeeded);\r
+ PhysicalAddressBits = 36;\r
}\r
- DEBUG ((EFI_D_ERROR, "TotalPageTableSize - %x pages\n", TotalPageTableSize));\r
- \r
+ }\r
+\r
+ //\r
+ // IA-32e paging translates 48-bit linear addresses to 52-bit physical addresses.\r
+ //\r
+ ASSERT (PhysicalAddressBits <= 52);\r
+ if (PhysicalAddressBits > 48) {\r
+ PhysicalAddressBits = 48;\r
+ }\r
+\r
+ ExtraPageTablePages = 0;\r
+ if (!LongModeWakingVectorSupport) {\r
//\r
- // By architecture only one PageMapLevel4 exists - so lets allocate storage for it.\r
+ // Create 4G page table when BIOS does not support long mode waking vector,\r
+ // and let PF handler to handle > 4G request.\r
//\r
- S3NvsPageTableAddress = (EFI_PHYSICAL_ADDRESS)(UINTN)AllocateMemoryBelow4G (EfiReservedMemoryType, EFI_PAGES_TO_SIZE(TotalPageTableSize));\r
- ASSERT (S3NvsPageTableAddress != 0);\r
- PcdSet64 (PcdIdentifyMappingPageTablePtr, S3NvsPageTableAddress); \r
- return S3NvsPageTableAddress;\r
+ PhysicalAddressBits = 32;\r
+ ExtraPageTablePages = EXTRA_PAGE_TABLE_PAGES;\r
+ }\r
+\r
+ //\r
+ // Calculate the table entries needed.\r
+ //\r
+ if (PhysicalAddressBits <= 39 ) {\r
+ NumberOfPml4EntriesNeeded = 1;\r
+ NumberOfPdpEntriesNeeded = (UINT32)LShiftU64 (1, (PhysicalAddressBits - 30));\r
+ } else {\r
+ NumberOfPml4EntriesNeeded = (UINT32)LShiftU64 (1, (PhysicalAddressBits - 39));\r
+ NumberOfPdpEntriesNeeded = 512;\r
}\r
+\r
+ //\r
+ // We need calculate whole page size then allocate once, because S3 restore page table does not know each page in Nvs.\r
+ //\r
+ if (!Page1GSupport) {\r
+ TotalPageTableSize = (UINTN)(1 + NumberOfPml4EntriesNeeded + NumberOfPml4EntriesNeeded * NumberOfPdpEntriesNeeded);\r
+ } else {\r
+ TotalPageTableSize = (UINTN)(1 + NumberOfPml4EntriesNeeded);\r
+ }\r
+\r
+ TotalPageTableSize += ExtraPageTablePages;\r
+ DEBUG ((EFI_D_ERROR, "AcpiS3Save TotalPageTableSize - 0x%x pages\n", TotalPageTableSize));\r
+\r
+ //\r
+ // By architecture only one PageMapLevel4 exists - so lets allocate storage for it.\r
+ //\r
+ S3NvsPageTableAddress = (EFI_PHYSICAL_ADDRESS)(UINTN)AllocateMemoryBelow4G (EfiReservedMemoryType, EFI_PAGES_TO_SIZE(TotalPageTableSize));\r
+ ASSERT (S3NvsPageTableAddress != 0);\r
+ return S3NvsPageTableAddress;\r
} else {\r
//\r
// If DXE is running 32-bit mode, no need to establish page table.\r
STATIC BOOLEAN AlreadyEntered;\r
IA32_DESCRIPTOR *Idtr;\r
IA32_IDT_GATE_DESCRIPTOR *IdtGate;\r
+ EFI_ACPI_4_0_FIRMWARE_ACPI_CONTROL_STRUCTURE *Facs;\r
\r
DEBUG ((EFI_D_INFO, "S3Ready!\n"));\r
\r
//\r
// Get ACPI Table because we will save its position to variable\r
//\r
- AcpiS3Context->AcpiFacsTable = (EFI_PHYSICAL_ADDRESS)(UINTN)FindAcpiFacsTable ();\r
+ Facs = (EFI_ACPI_4_0_FIRMWARE_ACPI_CONTROL_STRUCTURE *) FindAcpiFacsTable ();\r
+ AcpiS3Context->AcpiFacsTable = (EFI_PHYSICAL_ADDRESS) (UINTN) Facs;\r
ASSERT (AcpiS3Context->AcpiFacsTable != 0);\r
\r
IdtGate = AllocateMemoryBelow4G (EfiReservedMemoryType, sizeof(IA32_IDT_GATE_DESCRIPTOR) * 0x100 + sizeof(IA32_DESCRIPTOR));\r
//\r
// Allocate page table\r
//\r
- AcpiS3Context->S3NvsPageTableAddress = S3CreateIdentityMappingPageTables ();\r
+ AcpiS3Context->S3NvsPageTableAddress = S3AllocatePageTablesBuffer (IsLongModeWakingVectorSupport (Facs));\r
\r
//\r
// Allocate stack\r