IntelFsp2Pkg: FspSecCore support for X64

[mirror_edk2.git] / IntelFsp2Pkg / FspSecCore / Ia32 / FspApiEntryCommon.nasm

diff --git a/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryCommon.nasm b/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryCommon.nasm
index 26ae7d9fd36daaeb60678fb98864f95d193ee6bb..8d8deba28a9a096ba4eed0502ebe68f7d106f2d4 100644 (file)
--- a/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryCommon.nasm
+++ b/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryCommon.nasm
@@ -1,12 +1,14 @@
 ;; @file\r
 ;  Provide FSP API entry points.\r
 ;\r
-; Copyright (c) 2016 - 2020, Intel Corporation. All rights reserved.<BR>\r
+; Copyright (c) 2016 - 2022, Intel Corporation. All rights reserved.<BR>\r
 ; SPDX-License-Identifier: BSD-2-Clause-Patent\r
 ;;\r
 \r
     SECTION .text\r
 \r
+STACK_SAVED_EAX_OFFSET       EQU   4 * 7 ; size of a general purpose register * eax index\r
+\r
 ;\r
 ; Following functions will be provided in C\r
 ;\r
@@ -52,7 +54,7 @@ FspApiCommon1:
   add    esp, 8\r
   cmp    eax, 0\r
   jz     FspApiCommon2\r
-  mov    dword  [esp + (4 * 7)], eax\r
+  mov    dword  [esp + STACK_SAVED_EAX_OFFSET], eax\r
   popad\r
 exit:\r
   ret\r