Add IntelFsp2Pkg and IntelFsp2WrapperPkg.

[mirror_edk2.git] / IntelFsp2Pkg / FspSecCore / Ia32 / InitializeFpu.nasm

diff --git a/IntelFsp2Pkg/FspSecCore/Ia32/InitializeFpu.nasm b/IntelFsp2Pkg/FspSecCore/Ia32/InitializeFpu.nasm
new file mode 100644 (file)
index 0000000..cc87e89
--- /dev/null
+++ b/IntelFsp2Pkg/FspSecCore/Ia32/InitializeFpu.nasm
@@ -0,0 +1,78 @@
+;------------------------------------------------------------------------------\r
+;\r
+; Copyright (c) 2015, Intel Corporation. All rights reserved.<BR>\r
+; This program and the accompanying materials\r
+; are licensed and made available under the terms and conditions of the BSD License\r
+; which accompanies this distribution.  The full text of the license may be found at\r
+; http://opensource.org/licenses/bsd-license.php.\r
+;\r
+; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+;\r
+; Abstract:\r
+;\r
+;------------------------------------------------------------------------------\r
+\r
+\r
+SECTION .data\r
+;\r
+; Float control word initial value:\r
+; all exceptions masked, double-precision, round-to-nearest\r
+;\r
+ASM_PFX(mFpuControlWord):\r
+    dw    0x027F\r
+;\r
+; Multimedia-extensions control word:\r
+; all exceptions masked, round-to-nearest, flush to zero for masked underflow\r
+;\r
+ASM_PFX(mMmxControlWord):\r
+     dd     0x01F80\r
+\r
+SECTION .text\r
+\r
+;\r
+; Initializes floating point units for requirement of UEFI specification.\r
+;\r
+; This function initializes floating-point control word to 0x027F (all exceptions\r
+; masked,double-precision, round-to-nearest) and multimedia-extensions control word\r
+; (if supported) to 0x1F80 (all exceptions masked, round-to-nearest, flush to zero\r
+; for masked underflow).\r
+;\r
+\r
+global ASM_PFX(InitializeFloatingPointUnits)\r
+ASM_PFX(InitializeFloatingPointUnits):\r
+\r
+\r
+    push    ebx\r
+\r
+    ;\r
+    ; Initialize floating point units\r
+    ;\r
+    finit\r
+    fldcw    [ASM_PFX(mFpuControlWord)]\r
+\r
+    ;\r
+    ; Use CpuId instructuion (CPUID.01H:EDX.SSE[bit 25] = 1) to test\r
+    ; whether the processor supports SSE instruction.\r
+    ;\r
+    mov     eax, 1\r
+    cpuid\r
+    bt      edx, 25\r
+    jnc     Done\r
+\r
+    ;\r
+    ; Set OSFXSR bit 9 in CR4\r
+    ;\r
+    mov     eax, cr4\r
+    or      eax, BIT9\r
+    mov     cr4, eax\r
+\r
+    ;\r
+    ; The processor should support SSE instruction and we can use\r
+    ; ldmxcsr instruction\r
+    ;\r
+    ldmxcsr [ASM_PFX(mMmxControlWord)]\r
+Done:\r
+    pop     ebx\r
+\r
+    ret\r