IntelFsp2Pkg: Adopt FSP 2.3 specification.

[mirror_edk2.git] / IntelFsp2Pkg / Include / Guid / FspHeaderFile.h

diff --git a/IntelFsp2Pkg/Include/Guid/FspHeaderFile.h b/IntelFsp2Pkg/Include/Guid/FspHeaderFile.h
index 96cac001249479e6f5a011488f398495bb5ee22d..11e0ede65b42be73866473779a111fa48615b014 100644 (file)
--- a/IntelFsp2Pkg/Include/Guid/FspHeaderFile.h
+++ b/IntelFsp2Pkg/Include/Guid/FspHeaderFile.h
@@ -1,15 +1,9 @@
 /** @file\r
   Intel FSP Header File definition from Intel Firmware Support Package External\r
-  Architecture Specification v2.0.\r
+  Architecture Specification v2.0 and above.\r
 \r
-  Copyright (c) 2014 - 2016, Intel Corporation. All rights reserved.<BR>\r
-  This program and the accompanying materials\r
-  are licensed and made available under the terms and conditions of the BSD License\r
-  which accompanies this distribution.  The full text of the license may be found at\r
-  http://opensource.org/licenses/bsd-license.php.\r
-\r
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+  Copyright (c) 2014 - 2021, Intel Corporation. All rights reserved.<BR>\r
+  SPDX-License-Identifier: BSD-2-Clause-Patent\r
 \r
 **/\r
 \r
@@ -50,14 +44,28 @@ typedef struct {
   UINT8   Reserved1[2];\r
   ///\r
   /// Byte 0x0A: Indicates compliance with a revision of this specification in the BCD format.\r
+  ///            For revision v2.3 the value will be 0x23.\r
   ///\r
   UINT8   SpecVersion;\r
   ///\r
   /// Byte 0x0B: Revision of the FSP Information Header.\r
+  ///            The Current value for this field is 0x6.\r
   ///\r
   UINT8   HeaderRevision;\r
   ///\r
   /// Byte 0x0C: Revision of the FSP binary.\r
+  ///            Major.Minor.Revision.Build\r
+  ///            If FSP HeaderRevision is <= 5, the ImageRevision can be decoded as follows:\r
+  ///               7 : 0  - Build Number\r
+  ///              15 : 8  - Revision\r
+  ///              23 : 16 - Minor Version\r
+  ///              31 : 24 - Major Version\r
+  ///            If FSP HeaderRevision is >= 6, ImageRevision specifies the low-order bytes of the build number and revision\r
+  ///            while ExtendedImageRevision specifies the high-order bytes of the build number and revision.\r
+  ///               7 : 0  - Low Byte of Build Number\r
+  ///              15 : 8  - Low Byte of Revision\r
+  ///              23 : 16 - Minor Version\r
+  ///              31 : 24 - Major Version\r
   ///\r
   UINT32  ImageRevision;\r
   ///\r
@@ -116,6 +124,29 @@ typedef struct {
   /// Byte 0x44: The offset for the API to initialize the CPU and chipset.\r
   ///\r
   UINT32  FspSiliconInitEntryOffset;\r
+  ///\r
+  /// Byte 0x48: Offset for the API for the optional Multi-Phase processor and chipset initialization.\r
+  ///            This value is only valid if FSP HeaderRevision is >= 5.\r
+  ///            If the value is set to 0x00000000, then this API is not available in this component.\r
+  ///\r
+  UINT32  FspMultiPhaseSiInitEntryOffset;\r
+  ///\r
+  /// Byte 0x4C: Extended revision of the FSP binary.\r
+  ///            This value is only valid if FSP HeaderRevision is >= 6.\r
+  ///            ExtendedImageRevision specifies the high-order byte of the revision and build number in the FSP binary revision.\r
+  ///               7 : 0 - High Byte of Build Number\r
+  ///              15 : 8 - High Byte of Revision\r
+  ///            The FSP binary build number can be decoded as follows:\r
+  ///            Build Number = (ExtendedImageRevision[7:0] << 8) | ImageRevision[7:0]\r
+  ///            Revision = (ExtendedImageRevision[15:8] << 8) | ImageRevision[15:8]\r
+  ///            Minor Version = ImageRevision[23:16]\r
+  ///            Major Version = ImageRevision[31:24]\r
+  ///\r
+  UINT16  ExtendedImageRevision;\r
+  ///\r
+  /// Byte 0x4E: Reserved4.\r
+  ///\r
+  UINT16  Reserved4;\r
 } FSP_INFO_HEADER;\r
 \r
 ///\r
@@ -144,7 +175,7 @@ typedef struct {
   ///\r
   UINT8   Reserved;\r
   ///\r
-  /// Byte 0x0A: FSP producer identification string \r
+  /// Byte 0x0A: FSP producer identification string\r
   ///\r
   CHAR8   FspProducerId[6];\r
   ///\r