## @file\r
# Provides driver and definitions to build fsp in EDKII bios.\r
#\r
-# Copyright (c) 2014 - 2016, Intel Corporation. All rights reserved.<BR>\r
-# This program and the accompanying materials are licensed and made available under\r
-# the terms and conditions of the BSD License that accompanies this distribution.\r
-# The full text of the license may be found at\r
-# http://opensource.org/licenses/bsd-license.php.\r
-#\r
-# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
-# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+# Copyright (c) 2014 - 2019, Intel Corporation. All rights reserved.<BR>\r
+# SPDX-License-Identifier: BSD-2-Clause-Patent\r
#\r
##\r
\r
\r
[Includes]\r
Include\r
- \r
+\r
[LibraryClasses]\r
## @libraryclass Provides cache-as-ram support.\r
CacheAsRamLib|Include/Library/CacheAsRamLib.h\r
\r
## @libraryclass Provides FSP switch stack function.\r
FspSwitchStackLib|Include/Library/FspSwitchStackLib.h\r
- \r
+\r
## @libraryclass Provides FSP platform sec related actions.\r
FspSecPlatformLib|Include/Library/FspSecPlatformLib.h\r
\r
+[Ppis]\r
+ #\r
+ # PPI to indicate FSP is ready to enter notify phase\r
+ # This provides flexibility for any late initialization that must be done right before entering notify phase.\r
+ #\r
+ gFspReadyForNotifyPhasePpiGuid = { 0xcd167c1e, 0x6e0b, 0x42b3, {0x82, 0xf6, 0xe3, 0xe9, 0x06, 0x19, 0x98, 0x10}}\r
+\r
+ #\r
+ # PPI as dependency on some modules which only required for API mode\r
+ #\r
+ gFspInApiModePpiGuid = { 0xa1eeab87, 0xc859, 0x479d, {0x89, 0xb5, 0x14, 0x61, 0xf4, 0x06, 0x1a, 0x3e}}\r
+\r
+ #\r
+ # PPI for Architectural configuration data for FSP-M\r
+ #\r
+ gFspmArchConfigPpiGuid = { 0x824d5a3a, 0xaf92, 0x4c0c, {0x9f, 0x19, 0x19, 0x52, 0x6d, 0xca, 0x4a, 0xbb}}\r
+\r
+ #\r
+ # PPI to tear down the temporary memory set up by TempRamInit ().\r
+ #\r
+ gFspTempRamExitPpiGuid = { 0xbc1cfbdb, 0x7e50, 0x42be, {0xb4, 0x87, 0x22, 0xe0, 0xa9, 0x0c, 0xb0, 0x52}}\r
+\r
[Guids]\r
#\r
# GUID defined in package\r
gIntelFsp2PkgTokenSpaceGuid.PcdFspBootFirmwareVolumeBase|0xFFF80000|UINT32|0x10000003\r
gIntelFsp2PkgTokenSpaceGuid.PcdFspHeaderSpecVersion | 0x20| UINT8|0x00000002\r
\r
+ #\r
# x % of FSP temporary memory will be used for heap\r
# (100 - x) % of FSP temporary memory will be used for stack\r
+ # 0 means FSP will share the stack with boot loader and FSP temporary memory is heap\r
+ # Note: This mode assumes boot loader stack is large enough for FSP to use.\r
+ #\r
gIntelFsp2PkgTokenSpaceGuid.PcdFspHeapSizePercentage | 50| UINT8|0x10000004\r
- \r
+ #\r
+ # Maximal Interrupt supported in IDT table.\r
+ #\r
+ gIntelFsp2PkgTokenSpaceGuid.PcdFspMaxInterruptSupported | 34| UINT8|0x10000005\r
+\r
[PcdsFixedAtBuild,PcdsDynamic,PcdsDynamicEx]\r
gIntelFsp2PkgTokenSpaceGuid.PcdFspReservedMemoryLength |0x00100000|UINT32|0x46530000\r
gIntelFsp2PkgTokenSpaceGuid.PcdBootLoaderEntry |0xFFFFFFE4|UINT32|0x46530100\r