IntelFsp2WrapperPkg : FSPM/S UPD data address based on Build Type

[mirror_edk2.git] / IntelFsp2WrapperPkg / FspmWrapperPeim / FspmWrapperPeim.c

diff --git a/IntelFsp2WrapperPkg/FspmWrapperPeim/FspmWrapperPeim.c b/IntelFsp2WrapperPkg/FspmWrapperPeim/FspmWrapperPeim.c
index 287e7f915964b80e145b65eecd2a5102739386e4..49fbb27eca948827cb208039d998a0400add178a 100644 (file)
--- a/IntelFsp2WrapperPkg/FspmWrapperPeim/FspmWrapperPeim.c
+++ b/IntelFsp2WrapperPkg/FspmWrapperPeim/FspmWrapperPeim.c
@@ -3,7 +3,7 @@
   register TemporaryRamDonePpi to call TempRamExit API, and register MemoryDiscoveredPpi\r
   notify to call FspSiliconInit API.\r
 \r
-  Copyright (c) 2014 - 2020, Intel Corporation. All rights reserved.<BR>\r
+  Copyright (c) 2014 - 2021, Intel Corporation. All rights reserved.<BR>\r
   SPDX-License-Identifier: BSD-2-Clause-Patent\r
 \r
 **/\r
@@ -38,6 +38,25 @@
 \r
 extern EFI_GUID  gFspHobGuid;\r
 \r
+/**\r
+  Get the FSP M UPD Data address\r
+\r
+  @return FSP-M UPD Data Address\r
+**/\r
+\r
+UINTN\r
+EFIAPI\r
+GetFspmUpdDataAddress (\r
+  VOID\r
+  )\r
+{\r
+  if (PcdGet64 (PcdFspmUpdDataAddress64) != 0) {\r
+    return (UINTN) PcdGet64 (PcdFspmUpdDataAddress64);\r
+  } else {\r
+    return (UINTN) PcdGet32 (PcdFspmUpdDataAddress);\r
+  }\r
+}\r
+\r
 /**\r
   Call FspMemoryInit API.\r
 \r
@@ -67,7 +86,7 @@ PeiFspMemoryInit (
     return EFI_DEVICE_ERROR;\r
   }\r
 \r
-  if ((PcdGet32 (PcdFspmUpdDataAddress) == 0) && (FspmHeaderPtr->CfgRegionSize != 0) && (FspmHeaderPtr->CfgRegionOffset != 0)) {\r
+  if ((GetFspmUpdDataAddress () == 0) && (FspmHeaderPtr->CfgRegionSize != 0) && (FspmHeaderPtr->CfgRegionOffset != 0)) {\r
     //\r
     // Copy default FSP-M UPD data from Flash\r
     //\r
@@ -79,7 +98,7 @@ PeiFspMemoryInit (
     //\r
     // External UPD is ready, get the buffer from PCD pointer.\r
     //\r
-    FspmUpdDataPtr = (FSPM_UPD_COMMON *)PcdGet32 (PcdFspmUpdDataAddress);\r
+    FspmUpdDataPtr = (FSPM_UPD_COMMON *) GetFspmUpdDataAddress();\r
     ASSERT (FspmUpdDataPtr != NULL);\r
   }\r
 \r