register TemporaryRamDonePpi to call TempRamExit API, and register MemoryDiscoveredPpi\r
notify to call FspSiliconInit API.\r
\r
- Copyright (c) 2014 - 2020, Intel Corporation. All rights reserved.<BR>\r
+ Copyright (c) 2014 - 2021, Intel Corporation. All rights reserved.<BR>\r
SPDX-License-Identifier: BSD-2-Clause-Patent\r
\r
**/\r
#include <Library/MemoryAllocationLib.h>\r
#include <Library/FspWrapperPlatformLib.h>\r
#include <Library/FspWrapperHobProcessLib.h>\r
+#include <Library/FspWrapperMultiPhaseProcessLib.h>\r
#include <Library/TimerLib.h>\r
#include <Library/PerformanceLib.h>\r
#include <Library/FspWrapperApiLib.h>\r
#include <Library/FspWrapperApiTestLib.h>\r
#include <FspEas.h>\r
#include <FspStatusCode.h>\r
+#include <FspGlobalData.h>\r
\r
extern EFI_PEI_NOTIFY_DESCRIPTOR mS3EndOfPeiNotifyDesc;\r
extern EFI_GUID gFspHobGuid;\r
//\r
if ((Status >= FSP_STATUS_RESET_REQUIRED_COLD) && (Status <= FSP_STATUS_RESET_REQUIRED_8)) {\r
DEBUG ((DEBUG_INFO, "FSP S3NotifyPhase AfterPciEnumeration requested reset 0x%x\n", Status));\r
- CallFspWrapperResetSystem ((UINT32)Status);\r
+ CallFspWrapperResetSystem (Status);\r
}\r
\r
NotifyPhaseParams.Phase = EnumInitPhaseReadyToBoot;\r
//\r
if ((Status >= FSP_STATUS_RESET_REQUIRED_COLD) && (Status <= FSP_STATUS_RESET_REQUIRED_8)) {\r
DEBUG ((DEBUG_INFO, "FSP S3NotifyPhase ReadyToBoot requested reset 0x%x\n", Status));\r
- CallFspWrapperResetSystem ((UINT32)Status);\r
+ CallFspWrapperResetSystem (Status);\r
}\r
\r
NotifyPhaseParams.Phase = EnumInitPhaseEndOfFirmware;\r
//\r
if ((Status >= FSP_STATUS_RESET_REQUIRED_COLD) && (Status <= FSP_STATUS_RESET_REQUIRED_8)) {\r
DEBUG ((DEBUG_INFO, "FSP S3NotifyPhase EndOfFirmware requested reset 0x%x\n", Status));\r
- CallFspWrapperResetSystem ((UINT32)Status);\r
+ CallFspWrapperResetSystem (Status);\r
}\r
\r
return EFI_SUCCESS;\r
}\r
}\r
\r
+/**\r
+ Get the FSP S UPD Data address\r
+\r
+ @return FSP-S UPD Data Address\r
+**/\r
+UINTN\r
+GetFspsUpdDataAddress (\r
+ VOID\r
+ )\r
+{\r
+ if (PcdGet64 (PcdFspsUpdDataAddress64) != 0) {\r
+ return (UINTN)PcdGet64 (PcdFspsUpdDataAddress64);\r
+ } else {\r
+ return (UINTN)PcdGet32 (PcdFspsUpdDataAddress);\r
+ }\r
+}\r
+\r
/**\r
This function is for FSP dispatch mode to perform post FSP-S process.\r
\r
return EFI_DEVICE_ERROR;\r
}\r
\r
- if ((PcdGet32 (PcdFspsUpdDataAddress) == 0) && (FspsHeaderPtr->CfgRegionSize != 0) && (FspsHeaderPtr->CfgRegionOffset != 0)) {\r
+ if ((GetFspsUpdDataAddress () == 0) && (FspsHeaderPtr->CfgRegionSize != 0) && (FspsHeaderPtr->CfgRegionOffset != 0)) {\r
//\r
// Copy default FSP-S UPD data from Flash\r
//\r
SourceData = (UINTN *)((UINTN)FspsHeaderPtr->ImageBase + (UINTN)FspsHeaderPtr->CfgRegionOffset);\r
CopyMem (FspsUpdDataPtr, SourceData, (UINTN)FspsHeaderPtr->CfgRegionSize);\r
} else {\r
- FspsUpdDataPtr = (FSPS_UPD_COMMON *)PcdGet32 (PcdFspsUpdDataAddress);\r
+ FspsUpdDataPtr = (FSPS_UPD_COMMON *)GetFspsUpdDataAddress ();\r
ASSERT (FspsUpdDataPtr != NULL);\r
}\r
\r
TimeStampCounterStart = AsmReadTsc ();\r
PERF_START_EX (&gFspApiPerformanceGuid, "EventRec", NULL, 0, FSP_STATUS_CODE_SILICON_INIT | FSP_STATUS_CODE_COMMON_CODE | FSP_STATUS_CODE_API_ENTRY);\r
Status = CallFspSiliconInit ((VOID *)FspsUpdDataPtr);\r
- PERF_END_EX (&gFspApiPerformanceGuid, "EventRec", NULL, 0, FSP_STATUS_CODE_SILICON_INIT | FSP_STATUS_CODE_COMMON_CODE | FSP_STATUS_CODE_API_EXIT);\r
- DEBUG ((DEBUG_INFO, "Total time spent executing FspSiliconInitApi: %d millisecond\n", DivU64x32 (GetTimeInNanoSecond (AsmReadTsc () - TimeStampCounterStart), 1000000)));\r
\r
//\r
// Reset the system if FSP API returned FSP_STATUS_RESET_REQUIRED status\r
//\r
if ((Status >= FSP_STATUS_RESET_REQUIRED_COLD) && (Status <= FSP_STATUS_RESET_REQUIRED_8)) {\r
- DEBUG ((DEBUG_INFO, "FspSiliconInitApi requested reset 0x%x\n", Status));\r
- CallFspWrapperResetSystem ((UINT32)Status);\r
+ DEBUG ((DEBUG_INFO, "FspSiliconInitApi requested reset %r\n", Status));\r
+ CallFspWrapperResetSystem (Status);\r
}\r
\r
- if (EFI_ERROR (Status)) {\r
+ if ((Status != FSP_STATUS_VARIABLE_REQUEST) && EFI_ERROR (Status)) {\r
DEBUG ((DEBUG_ERROR, "ERROR - Failed to execute FspSiliconInitApi(), Status = %r\n", Status));\r
+ ASSERT_EFI_ERROR (Status);\r
}\r
\r
- DEBUG ((DEBUG_INFO, "FspSiliconInit status: 0x%x\n", Status));\r
- ASSERT_EFI_ERROR (Status);\r
+ DEBUG ((DEBUG_INFO, "FspSiliconInit status: %r\n", Status));\r
+\r
+ if (Status == FSP_STATUS_VARIABLE_REQUEST) {\r
+ //\r
+ // call to Variable request handler\r
+ //\r
+ FspWrapperVariableRequestHandler (&FspHobListPtr, FspMultiPhaseSiInitApiIndex);\r
+ }\r
+\r
+ //\r
+ // See if MultiPhase process is required or not\r
+ //\r
+ FspWrapperMultiPhaseHandler (&FspHobListPtr, FspMultiPhaseSiInitApiIndex); // FspS MultiPhase\r
+\r
+ PERF_END_EX (&gFspApiPerformanceGuid, "EventRec", NULL, 0, FSP_STATUS_CODE_SILICON_INIT | FSP_STATUS_CODE_COMMON_CODE | FSP_STATUS_CODE_API_EXIT);\r
+ DEBUG ((DEBUG_INFO, "Total time spent executing FspSiliconInitApi: %d millisecond\n", DivU64x32 (GetTimeInNanoSecond (AsmReadTsc () - TimeStampCounterStart), 1000000)));\r
\r
Status = TestFspSiliconInitApiOutput ((VOID *)NULL);\r
if (RETURN_ERROR (Status)) {\r