## @file\r
# Provides drivers and definitions to support fsp in EDKII bios.\r
#\r
-# Copyright (c) 2014 - 2016, Intel Corporation. All rights reserved.<BR>\r
-# This program and the accompanying materials are licensed and made available under\r
-# the terms and conditions of the BSD License that accompanies this distribution.\r
-# The full text of the license may be found at\r
-# http://opensource.org/licenses/bsd-license.php.\r
-#\r
-# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
-# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+# Copyright (c) 2014 - 2022, Intel Corporation. All rights reserved.<BR>\r
+# SPDX-License-Identifier: BSD-2-Clause-Patent\r
#\r
##\r
\r
## @libraryclass Provide FSP platform related function.\r
FspWrapperPlatformLib|Include/Library/FspWrapperPlatformLib.h\r
\r
+ ## @libraryclass Provide FSP TPM measurement related function.\r
+ FspMeasurementLib|Include/Library/FspMeasurementLib.h\r
+\r
+ ## @libraryclass Provide MultiPhase handling related functions.\r
+ FspWrapperMultiPhaseProcessLib|Include/Library/FspWrapperMultiPhaseProcessLib.h\r
+\r
+ ## @libraryclass Provide MultiPhase platform actions related functions.\r
+ FspWrapperPlatformMultiPhaseLib|Include/Library/FspWrapperPlatformMultiPhaseLib.h\r
+\r
+\r
[Guids]\r
#\r
# GUID defined in package\r
## Provides the size of the BIOS Flash Device.\r
gIntelFsp2WrapperTokenSpaceGuid.PcdFlashCodeCacheSize|0x00200000|UINT32|0x10000002\r
\r
- ## Indicates the base address of the first Microcode Patch in the Microcode Region\r
- gIntelFsp2WrapperTokenSpaceGuid.PcdCpuMicrocodePatchAddress|0x0|UINT64|0x10000005\r
- gIntelFsp2WrapperTokenSpaceGuid.PcdCpuMicrocodePatchRegionSize|0x0|UINT64|0x10000006\r
- ## Indicates the offset of the Cpu Microcode.\r
- gIntelFsp2WrapperTokenSpaceGuid.PcdFlashMicrocodeOffset|0x90|UINT32|0x10000007\r
-\r
## Indicate the PEI memory size platform want to report\r
gIntelFsp2WrapperTokenSpaceGuid.PcdPeiMinMemSize|0x1800000|UINT32|0x40000004\r
## Indicate the PEI memory size platform want to report\r
gIntelFsp2WrapperTokenSpaceGuid.PcdPeiRecoveryMinMemSize|0x3000000|UINT32|0x40000005\r
\r
- ## This is the base address of FSP-T/M/S\r
+ ## This is the base address of FSP-T\r
gIntelFsp2WrapperTokenSpaceGuid.PcdFsptBaseAddress|0x00000000|UINT32|0x00000300\r
- gIntelFsp2WrapperTokenSpaceGuid.PcdFspmBaseAddress|0x00000000|UINT32|0x00000301\r
+\r
+ ## This PCD indicates if FSP APIs are skipped from FSP wrapper.<BR><BR>\r
+ # If a bit is set, that means this FSP API is skipped.<BR>\r
+ # If a bit is clear, that means this FSP API is NOT skipped.<BR>\r
+ # NOTE: Only NotifyPhase Post PCI enumeration (BIT16) is implemented.<BR>\r
+ # BIT[15:0] is for function:<BR>\r
+ # BIT0 - Skip TempRamInit<BR>\r
+ # BIT1 - Skip MemoryInit<BR>\r
+ # BIT2 - Skip TempRamExit<BR>\r
+ # BIT3 - Skip SiliconInit<BR>\r
+ # BIT4 - Skip NotifyPhase<BR>\r
+ # BIT[32:16] is for sub-function:<BR>\r
+ # BIT16 - Skip NotifyPhase (AfterPciEnumeration)<BR>\r
+ # BIT17 - Skip NotifyPhase (ReadyToBoot)<BR>\r
+ # BIT18 - Skip NotifyPhase (EndOfFirmware)<BR>\r
+ # Any undefined BITs are reserved for future use.<BR>\r
+ # @Prompt Skip FSP API from FSP wrapper.\r
+ gIntelFsp2WrapperTokenSpaceGuid.PcdSkipFspApi|0x00000000|UINT32|0x40000009\r
+\r
+ ## This PCD decides how FSP is measured\r
+ # 1) The BootGuard ACM may already measured the FSP component, such as FSPT/FSPM.\r
+ # We need a flag (PCD) to indicate if there is need to do such FSP measurement or NOT.\r
+ # 2) The FSP binary includes FSP code and FSP UPD region. The UPD region is considered\r
+ # as configuration block, and it may be updated by OEM by design.\r
+ # This flag (PCD) is to indicate if we need isolate the UPD region from the FSP code region.\r
+ # BIT0: Need measure FSP. (for FSP1.x) - reserved in FSP2.\r
+ # BIT1: Need measure FSPT. (for FSP 2.x)\r
+ # BIT2: Need measure FSPM. (for FSP 2.x)\r
+ # BIT3: Need measure FSPS. (for FSP 2.x)\r
+ # BIT4~30: reserved.\r
+ # BIT31: Need isolate UPD region measurement.\r
+ #0: measure FSP[T|M|S] as one binary in one record (PCR0).\r
+ #1: measure FSP UPD region in one record (PCR1), the FSP code without UPD in another record (PCR0).\r
+ #\r
+ gIntelFsp2WrapperTokenSpaceGuid.PcdFspMeasurementConfig|0x00000000|UINT32|0x4000000B\r
\r
[PcdsFixedAtBuild, PcdsPatchableInModule,PcdsDynamic,PcdsDynamicEx]\r
+ ## This PCD decides how Wrapper code utilizes FSP\r
+ # 0: DISPATCH mode (FSP Wrapper will load PeiCore from FSP without calling FSP API)\r
+ # 1: API mode (FSP Wrapper will call FSP API)\r
+ #\r
+ gIntelFsp2WrapperTokenSpaceGuid.PcdFspModeSelection|0x00000001|UINT8|0x4000000A\r
+\r
+ #\r
+ ## These are the base address of FSP-M/S\r
+ #\r
+ gIntelFsp2WrapperTokenSpaceGuid.PcdFspmBaseAddress|0x00000000|UINT32|0x00001000\r
gIntelFsp2WrapperTokenSpaceGuid.PcdFspsBaseAddress|0x00000000|UINT32|0x00001001\r
-
\ No newline at end of file
+ #\r
+ # To provide flexibility for platform to pre-allocate FSP UPD buffer\r
+ #\r
+ # The PCDs define the pre-allocated FSPM and FSPS UPD Data Buffer Address.\r
+ # 0x00000000 - Platform will not pre-allocate UPD buffer before FspWrapper module\r
+ # non-zero - Platform will pre-allocate UPD buffer and patch this value to\r
+ # buffer address before FspWrapper module executing.\r
+ #\r
+ gIntelFsp2WrapperTokenSpaceGuid.PcdFspmUpdDataAddress|0x00000000|UINT32|0x50000000\r
+ gIntelFsp2WrapperTokenSpaceGuid.PcdFspsUpdDataAddress|0x00000000|UINT32|0x50000001\r
+ #\r
+ # Non-0 means PcdFspmUpdDataAddress will be ignored, otherwise PcdFspmUpdDataAddress will be used.\r
+ #\r
+ gIntelFsp2WrapperTokenSpaceGuid.PcdFspmUpdDataAddress64|0x00000000|UINT64|0x50000002\r
+ #\r
+ # Non-0 means PcdFspsUpdDataAddress will be ignored, otherwise PcdFspsUpdDataAddress will be used.\r
+ #\r
+ gIntelFsp2WrapperTokenSpaceGuid.PcdFspsUpdDataAddress64|0x00000000|UINT64|0x50000003\r
projects / mirror_edk2.git / blobdiff