IntelFsp2WrapperPkg: SecFspWrapperPlatformSecLibSample support for X64

[mirror_edk2.git] / IntelFsp2WrapperPkg / Library / SecFspWrapperPlatformSecLibSample / X64 / SecEntry.nasm

diff --git a/IntelFsp2WrapperPkg/Library/SecFspWrapperPlatformSecLibSample/X64/SecEntry.nasm b/IntelFsp2WrapperPkg/Library/SecFspWrapperPlatformSecLibSample/X64/SecEntry.nasm
new file mode 100644 (file)
index 0000000..dbbf633
--- /dev/null
+++ b/IntelFsp2WrapperPkg/Library/SecFspWrapperPlatformSecLibSample/X64/SecEntry.nasm
@@ -0,0 +1,171 @@
+;------------------------------------------------------------------------------\r
+;\r
+; Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>\r
+; SPDX-License-Identifier: BSD-2-Clause-Patent\r
+;\r
+; Module Name:\r
+;\r
+;  SecEntry.asm\r
+;\r
+; Abstract:\r
+;\r
+;  This is the code that calls TempRamInit API from FSP binary and passes\r
+;  control into PEI core.\r
+;\r
+;------------------------------------------------------------------------------\r
+\r
+#include "Fsp.h"\r
+\r
+IA32_CR4_OSFXSR           equ        200h\r
+IA32_CR4_OSXMMEXCPT       equ        400h\r
+IA32_CR0_MP               equ        2h\r
+\r
+IA32_CPUID_SSE2           equ        02000000h\r
+IA32_CPUID_SSE2_B         equ        26\r
+\r
+SECTION .text\r
+\r
+extern   ASM_PFX(CallPeiCoreEntryPoint)\r
+extern   ASM_PFX(FsptUpdDataPtr)\r
+\r
+; Pcds\r
+extern   ASM_PFX(PcdGet32 (PcdFsptBaseAddress))\r
+\r
+;----------------------------------------------------------------------------\r
+;\r
+; Procedure:    _ModuleEntryPoint\r
+;\r
+; Input:        None\r
+;\r
+; Output:       None\r
+;\r
+; Destroys:     Assume all registers\r
+;\r
+; Description:\r
+;\r
+;  Call TempRamInit API from FSP binary. After TempRamInit done, pass\r
+;  control into PEI core.\r
+;\r
+; Return:       None\r
+;\r
+;  MMX Usage:\r
+;              MM0 = BIST State\r
+;\r
+;----------------------------------------------------------------------------\r
+\r
+BITS 64\r
+align 16\r
+global ASM_PFX(ModuleEntryPoint)\r
+ASM_PFX(ModuleEntryPoint):\r
+  fninit                                ; clear any pending Floating point exceptions\r
+  ;\r
+  ; Store the BIST value in mm0\r
+  ;\r
+  movd    mm0, eax\r
+\r
+  ; Find the fsp info header\r
+  mov     rax, ASM_PFX(PcdGet32 (PcdFsptBaseAddress))\r
+  mov     edi, [eax]\r
+\r
+  mov     eax, dword [edi + FVH_SIGINATURE_OFFSET]\r
+  cmp     eax, FVH_SIGINATURE_VALID_VALUE\r
+  jnz     FspHeaderNotFound\r
+\r
+  xor     eax, eax\r
+  mov     ax, word [edi + FVH_EXTHEADER_OFFSET_OFFSET]\r
+  cmp     ax, 0\r
+  jnz     FspFvExtHeaderExist\r
+\r
+  xor     eax, eax\r
+  mov     ax, word [edi + FVH_HEADER_LENGTH_OFFSET]     ; Bypass Fv Header\r
+  add     edi, eax\r
+  jmp     FspCheckFfsHeader\r
+\r
+FspFvExtHeaderExist:\r
+  add     edi, eax\r
+  mov     eax, dword [edi + FVH_EXTHEADER_SIZE_OFFSET]  ; Bypass Ext Fv Header\r
+  add     edi, eax\r
+\r
+  ; Round up to 8 byte alignment\r
+  mov     eax, edi\r
+  and     al,  07h\r
+  jz      FspCheckFfsHeader\r
+\r
+  and     edi, 0FFFFFFF8h\r
+  add     edi, 08h\r
+\r
+FspCheckFfsHeader:\r
+  ; Check the ffs guid\r
+  mov     eax, dword [edi]\r
+  cmp     eax, FSP_HEADER_GUID_DWORD1\r
+  jnz     FspHeaderNotFound\r
+\r
+  mov     eax, dword [edi + 4]\r
+  cmp     eax, FSP_HEADER_GUID_DWORD2\r
+  jnz     FspHeaderNotFound\r
+\r
+  mov     eax, dword [edi + 8]\r
+  cmp     eax, FSP_HEADER_GUID_DWORD3\r
+  jnz     FspHeaderNotFound\r
+\r
+  mov     eax, dword [edi + 0Ch]\r
+  cmp     eax, FSP_HEADER_GUID_DWORD4\r
+  jnz     FspHeaderNotFound\r
+\r
+  add     edi, FFS_HEADER_SIZE_VALUE         ; Bypass the ffs header\r
+\r
+  ; Check the section type as raw section\r
+  mov     al, byte [edi + SECTION_HEADER_TYPE_OFFSET]\r
+  cmp     al, 019h\r
+  jnz FspHeaderNotFound\r
+\r
+  add     edi, RAW_SECTION_HEADER_SIZE_VALUE ; Bypass the section header\r
+  jmp     FspHeaderFound\r
+\r
+FspHeaderNotFound:\r
+  jmp     $\r
+\r
+FspHeaderFound:\r
+  ; Get the fsp TempRamInit Api address\r
+  mov     eax, dword [edi + FSP_HEADER_IMAGEBASE_OFFSET]\r
+  add     eax, dword [edi + FSP_HEADER_TEMPRAMINIT_OFFSET]\r
+\r
+  ; Setup the hardcode stack\r
+  mov     rsp, TempRamInitStack\r
+\r
+  ; Call the fsp TempRamInit Api\r
+  jmp     rax\r
+\r
+TempRamInitDone:\r
+  cmp     rax, 0800000000000000Eh ; Check if EFI_NOT_FOUND returned. Error code for Microcode Update not found.\r
+  je      CallSecFspInit          ; If microcode not found, don't hang, but continue.\r
+\r
+  cmp     rax, 0                  ; Check if EFI_SUCCESS returned.\r
+  jnz     FspApiFailed\r
+\r
+  ; RDX: start of range\r
+  ; R8: end of range\r
+CallSecFspInit:\r
+\r
+  mov     r8,  rdx\r
+  mov     rdx, rcx\r
+  xor     ecx, ecx ; zero - no Hob List Yet\r
+  mov     rsp, r8\r
+\r
+  ;\r
+  ; Per X64 calling convention, make sure RSP is 16-byte aligned.\r
+  ;\r
+  mov     rax, rsp\r
+  and     rax, 0fh\r
+  sub     rsp, rax\r
+\r
+  call    ASM_PFX(CallPeiCoreEntryPoint)\r
+\r
+FspApiFailed:\r
+  jmp     $\r
+\r
+align 10h\r
+TempRamInitStack:\r
+    DQ  TempRamInitDone\r
+    DQ  ASM_PFX(FsptUpdDataPtr)         ; TempRamInitParams\r
+\r