IntelFspPkg&IntelFspWrapperPkg: Remove them

[mirror_edk2.git] / IntelFspPkg / FspSecCore / Ia32 / SaveRestoreSse.inc

diff --git a/IntelFspPkg/FspSecCore/Ia32/SaveRestoreSse.inc b/IntelFspPkg/FspSecCore/Ia32/SaveRestoreSse.inc
deleted file mode 100644 (file)
index 6cbc3dd..0000000
--- a/IntelFspPkg/FspSecCore/Ia32/SaveRestoreSse.inc
+++ /dev/null
@@ -1,178 +0,0 @@
-;------------------------------------------------------------------------------\r
-;\r
-; Copyright (c) 2014 - 2015, Intel Corporation. All rights reserved.<BR>\r
-; SPDX-License-Identifier: BSD-2-Clause-Patent\r
-;\r
-; Abstract:\r
-;\r
-;   Provide macro for register save/restore using SSE registers\r
-;\r
-;------------------------------------------------------------------------------\r
-\r
-;\r
-; Define SSE instruction set\r
-;\r
-IFDEF USE_SSE41_FLAG\r
-;\r
-; Define SSE macros using SSE 4.1 instructions\r
-;\r
-SXMMN        MACRO   XMM, IDX, REG\r
-             pinsrd  XMM, REG, (IDX AND 3)\r
-             ENDM\r
-\r
-LXMMN        MACRO   XMM, REG, IDX\r
-             pextrd  REG, XMM, (IDX AND 3)\r
-             ENDM\r
-ELSE\r
-;\r
-; Define SSE macros using SSE 2 instructions\r
-;\r
-SXMMN        MACRO   XMM, IDX, REG\r
-             pinsrw  XMM, REG, (IDX AND 3) * 2\r
-             ror     REG, 16\r
-             pinsrw  XMM, REG, (IDX AND 3) * 2 + 1\r
-             rol     REG, 16\r
-             ENDM\r
-\r
-LXMMN        MACRO   XMM, REG, IDX\r
-             pshufd  XMM, XMM,  (0E4E4E4h SHR (IDX * 2))  AND 0FFh\r
-             movd    REG, XMM\r
-             pshufd  XMM, XMM,  (0E4E4E4h SHR (IDX * 2 + (IDX AND 1) * 4)) AND 0FFh\r
-             ENDM\r
-ENDIF\r
-\r
-;\r
-; XMM7 to save/restore EBP, EBX, ESI, EDI\r
-; \r
-SAVE_REGS    MACRO\r
-  SXMMN      xmm7, 0, ebp\r
-  SXMMN      xmm7, 1, ebx\r
-  SXMMN      xmm7, 2, esi\r
-  SXMMN      xmm7, 3, edi\r
-  SAVE_ESP\r
-             ENDM\r
-\r
-LOAD_REGS    MACRO\r
-  LXMMN      xmm7, ebp, 0\r
-  LXMMN      xmm7, ebx, 1\r
-  LXMMN      xmm7, esi, 2\r
-  LXMMN      xmm7, edi, 3\r
-  LOAD_ESP\r
-             ENDM\r
-\r
-;\r
-; XMM6 to save/restore EAX, EDX, ECX, ESP\r
-; \r
-LOAD_EAX     MACRO\r
-  LXMMN      xmm6, eax, 1\r
-             ENDM\r
-\r
-SAVE_EAX     MACRO\r
-  SXMMN      xmm6, 1, eax\r
-             ENDM\r
-\r
-LOAD_EDX     MACRO\r
-  LXMMN      xmm6, edx, 2\r
-             ENDM\r
-\r
-SAVE_EDX     MACRO\r
-  SXMMN      xmm6, 2, edx\r
-             ENDM\r
-\r
-SAVE_ECX     MACRO\r
-  SXMMN      xmm6, 3, ecx\r
-             ENDM\r
-\r
-LOAD_ECX     MACRO\r
-  LXMMN      xmm6, ecx, 3\r
-             ENDM\r
-\r
-SAVE_ESP     MACRO\r
-  SXMMN      xmm6, 0, esp\r
-             ENDM\r
-\r
-LOAD_ESP     MACRO\r
-  movd       esp,  xmm6\r
-             ENDM\r
-             \r
-;\r
-; XMM5 for calling stack\r
-;\r
-CALL_XMM     MACRO  Entry\r
-             local   ReturnAddress\r
-             mov     esi, offset ReturnAddress\r
-             pslldq  xmm5, 4\r
-IFDEF USE_SSE41_FLAG\r
-             pinsrd  xmm5, esi, 0\r
-ELSE             \r
-             pinsrw  xmm5, esi, 0\r
-             ror     esi,  16\r
-             pinsrw  xmm5, esi, 1                        \r
-ENDIF             \r
-             mov     esi,  Entry\r
-             jmp     esi\r
-ReturnAddress:             \r
-             ENDM\r
-            \r
-RET_XMM      MACRO               \r
-             movd    esi, xmm5\r
-             psrldq  xmm5, 4\r
-             jmp     esi\r
-             ENDM\r
-             \r
-ENABLE_SSE   MACRO\r
-            ;\r
-            ; Initialize floating point units\r
-            ;\r
-            local   NextAddress            \r
-            jmp     NextAddress\r
-ALIGN 4\r
-            ;\r
-            ; Float control word initial value:\r
-            ; all exceptions masked, double-precision, round-to-nearest\r
-            ;\r
-FpuControlWord       DW      027Fh\r
-            ;\r
-            ; Multimedia-extensions control word:\r
-            ; all exceptions masked, round-to-nearest, flush to zero for masked underflow\r
-            ;\r
-MmxControlWord       DD      01F80h \r
-SseError:      \r
-            ;\r
-            ; Processor has to support SSE\r
-            ;\r
-            jmp     SseError      \r
-NextAddress:            \r
-            finit\r
-            fldcw   FpuControlWord\r
-\r
-            ;\r
-            ; Use CpuId instructuion (CPUID.01H:EDX.SSE[bit 25] = 1) to test\r
-            ; whether the processor supports SSE instruction.\r
-            ;\r
-            mov     eax, 1\r
-            cpuid\r
-            bt      edx, 25\r
-            jnc     SseError\r
-\r
-IFDEF USE_SSE41_FLAG\r
-            ;\r
-            ; SSE 4.1 support\r
-            ;\r
-            bt      ecx, 19   \r
-            jnc     SseError\r
-ENDIF\r
-\r
-            ;\r
-            ; Set OSFXSR bit (bit #9) & OSXMMEXCPT bit (bit #10)\r
-            ;\r
-            mov     eax, cr4\r
-            or      eax, 00000600h\r
-            mov     cr4, eax\r
-\r
-            ;\r
-            ; The processor should support SSE instruction and we can use\r
-            ; ldmxcsr instruction\r
-            ;\r
-            ldmxcsr MmxControlWord\r
-            ENDM\r