MdeModulePkg/AtaAtapiPassThru: valid ports transverse algo of AHCI controller is...

[mirror_edk2.git] / MdeModulePkg / Bus / Ata / AtaAtapiPassThru / AhciMode.h

diff --git a/MdeModulePkg/Bus/Ata/AtaAtapiPassThru/AhciMode.h b/MdeModulePkg/Bus/Ata/AtaAtapiPassThru/AhciMode.h
index 9c4a9397e9a84400f60cebc158cae5602592abd4..485b64799eacb57a64a392e23f6dbb0b73b274d3 100644 (file)
--- a/MdeModulePkg/Bus/Ata/AtaAtapiPassThru/AhciMode.h
+++ b/MdeModulePkg/Bus/Ata/AtaAtapiPassThru/AhciMode.h
@@ -17,6 +17,8 @@
 #define EFI_AHCI_BAR_INDEX                     0x05\r
 \r
 #define EFI_AHCI_CAPABILITY_OFFSET             0x0000\r
+#define   EFI_AHCI_CAP_SSS                     BIT27\r
+#define   EFI_AHCI_CAP_S64A                    BIT31\r
 #define EFI_AHCI_GHC_OFFSET                    0x0004\r
 #define   EFI_AHCI_GHC_RESET                   BIT0\r
 #define   EFI_AHCI_GHC_IE                      BIT1\r
@@ -24,6 +26,8 @@
 #define EFI_AHCI_IS_OFFSET                     0x0008\r
 #define EFI_AHCI_PI_OFFSET                     0x000C\r
 \r
+#define EFI_AHCI_MAX_PORTS                     32\r
+\r
 typedef struct {\r
   UINT32  Lower32;\r
   UINT32  Upper32;\r
@@ -34,6 +38,19 @@ typedef union {
   UINT64    Uint64;\r
 } DATA_64;\r
 \r
+//\r
+// Refer SATA1.0a spec section 5.2, the Phy detection time should be less than 10ms.\r
+//\r
+#define  EFI_AHCI_BUS_PHY_DETECT_TIMEOUT       10\r
+//\r
+// Refer SATA1.0a spec, the FIS enable time should be less than 500ms.\r
+//\r
+#define  EFI_AHCI_PORT_CMD_FR_CLEAR_TIMEOUT    EFI_TIMER_PERIOD_MILLISECONDS(500)\r
+//\r
+// Refer SATA1.0a spec, the bus reset time should be less than 1s.\r
+//\r
+#define  EFI_AHCI_BUS_RESET_TIMEOUT            EFI_TIMER_PERIOD_SECONDS(1)\r
+\r
 #define  EFI_AHCI_ATAPI_DEVICE_SIG             0xEB140000\r
 #define  EFI_AHCI_ATA_DEVICE_SIG               0x00000000\r
 #define  EFI_AHCI_PORT_MULTIPLIER_SIG          0x96690000\r
@@ -103,7 +120,7 @@ typedef union {
 #define   EFI_AHCI_PORT_CMD_ST                 BIT0\r
 #define   EFI_AHCI_PORT_CMD_SUD                BIT1\r
 #define   EFI_AHCI_PORT_CMD_POD                BIT2\r
-#define   EFI_AHCI_PORT_CMD_COL                BIT3\r
+#define   EFI_AHCI_PORT_CMD_CLO                BIT3\r
 #define   EFI_AHCI_PORT_CMD_CR                 BIT15\r
 #define   EFI_AHCI_PORT_CMD_FRE                BIT4\r
 #define   EFI_AHCI_PORT_CMD_FR                 BIT14\r
@@ -312,7 +329,7 @@ AhciPacketCommandExecute (
   @param  PciIo              The PCI IO protocol instance.\r
   @param  Port               The number of port.\r
   @param  CommandSlot        The number of CommandSlot.\r
-  @param  Timeout            The timeout value of start.\r
+  @param  Timeout            The timeout value of start, uses 100ns as a unit.\r
    \r
   @retval EFI_DEVICE_ERROR   The command start unsuccessfully.\r
   @retval EFI_TIMEOUT        The operation is time out.\r
@@ -333,7 +350,7 @@ AhciStartCommand (
     \r
   @param  PciIo              The PCI IO protocol instance.\r
   @param  Port               The number of port.\r
-  @param  Timeout            The timeout value of stop.\r
+  @param  Timeout            The timeout value of stop, uses 100ns as a unit.\r
    \r
   @retval EFI_DEVICE_ERROR   The command stop unsuccessfully.\r
   @retval EFI_TIMEOUT        The operation is time out.\r