\r
This file contains the definination for host controller register operation routines.\r
\r
-Copyright (c) 2007 - 2010, Intel Corporation\r
-All rights reserved. This program and the accompanying materials\r
+Copyright (c) 2007 - 2012, Intel Corporation. All rights reserved.<BR>\r
+This program and the accompanying materials\r
are licensed and made available under the terms and conditions of the BSD License\r
which accompanies this distribution. The full text of the license may be found at\r
http://opensource.org/licenses/bsd-license.php\r
// Capability register bit definition\r
//\r
#define HCSP_NPORTS 0x0F // Number of root hub port\r
+#define HCSP_PPC 0x10 // Port Power Control\r
#define HCCP_64BIT 0x01 // 64-bit addressing capability\r
\r
//\r
//\r
#define EHC_BAR_INDEX 0 // how many bytes away from USB_BASE to 0x10\r
\r
+//\r
+// Debug port capability id\r
+//\r
+#define EHC_DEBUG_PORT_CAP_ID 0x0A\r
+\r
#define EHC_LINK_TERMINATED(Link) (((Link) & 0x01) != 0)\r
\r
#define EHC_ADDR(High, QhHw32) \\r
IN UINT32 Offset\r
);\r
\r
+/**\r
+ Read EHCI debug port register.\r
+\r
+ @param Ehc The EHCI device.\r
+ @param Offset Debug port register address.\r
+\r
+ @return The register content read.\r
+ @retval If err, return 0xffff.\r
+\r
+**/\r
+UINT32\r
+EhcReadDbgRegister (\r
+ IN USB2_HC_DEV *Ehc,\r
+ IN UINT32 Offset\r
+ );\r
\r
/**\r
Read EHCI Operation register.\r