\r
#include "Ehci.h"\r
\r
-\r
/**\r
Create helper QTD/QH for the EHCI device.\r
\r
**/\r
EFI_STATUS\r
EhcCreateHelpQ (\r
- IN USB2_HC_DEV *Ehc\r
+ IN USB2_HC_DEV *Ehc\r
)\r
{\r
- USB_ENDPOINT Ep;\r
- EHC_QH *Qh;\r
- QH_HW *QhHw;\r
- EHC_QTD *Qtd;\r
- EFI_PHYSICAL_ADDRESS PciAddr;\r
+ USB_ENDPOINT Ep;\r
+ EHC_QH *Qh;\r
+ QH_HW *QhHw;\r
+ EHC_QTD *Qtd;\r
+ EFI_PHYSICAL_ADDRESS PciAddr;\r
\r
//\r
// Create an inactive Qtd to terminate the short packet read.\r
return EFI_OUT_OF_RESOURCES;\r
}\r
\r
- Qtd->QtdHw.Status = QTD_STAT_HALTED;\r
- Ehc->ShortReadStop = Qtd;\r
+ Qtd->QtdHw.Status = QTD_STAT_HALTED;\r
+ Ehc->ShortReadStop = Qtd;\r
\r
//\r
// Create a QH to act as the EHC reclamation header.\r
// Set the header to loopback to itself.\r
//\r
- Ep.DevAddr = 0;\r
- Ep.EpAddr = 1;\r
- Ep.Direction = EfiUsbDataIn;\r
- Ep.DevSpeed = EFI_USB_SPEED_HIGH;\r
- Ep.MaxPacket = 64;\r
- Ep.HubAddr = 0;\r
- Ep.HubPort = 0;\r
- Ep.Toggle = 0;\r
- Ep.Type = EHC_BULK_TRANSFER;\r
- Ep.PollRate = 1;\r
-\r
- Qh = EhcCreateQh (Ehc, &Ep);\r
+ Ep.DevAddr = 0;\r
+ Ep.EpAddr = 1;\r
+ Ep.Direction = EfiUsbDataIn;\r
+ Ep.DevSpeed = EFI_USB_SPEED_HIGH;\r
+ Ep.MaxPacket = 64;\r
+ Ep.HubAddr = 0;\r
+ Ep.HubPort = 0;\r
+ Ep.Toggle = 0;\r
+ Ep.Type = EHC_BULK_TRANSFER;\r
+ Ep.PollRate = 1;\r
+\r
+ Qh = EhcCreateQh (Ehc, &Ep);\r
\r
if (Qh == NULL) {\r
return EFI_OUT_OF_RESOURCES;\r
\r
PciAddr = UsbHcGetPciAddressForHostMem (Ehc->MemPool, Qh, sizeof (EHC_QH));\r
QhHw = &Qh->QhHw;\r
- QhHw->HorizonLink = QH_LINK (PciAddr + OFFSET_OF(EHC_QH, QhHw), EHC_TYPE_QH, FALSE);\r
+ QhHw->HorizonLink = QH_LINK (PciAddr + OFFSET_OF (EHC_QH, QhHw), EHC_TYPE_QH, FALSE);\r
QhHw->Status = QTD_STAT_HALTED;\r
QhHw->ReclaimHead = 1;\r
Qh->NextQh = Qh;\r
//\r
// Create a dummy QH to act as the terminator for periodical schedule\r
//\r
- Ep.EpAddr = 2;\r
- Ep.Type = EHC_INT_TRANSFER_SYNC;\r
+ Ep.EpAddr = 2;\r
+ Ep.Type = EHC_INT_TRANSFER_SYNC;\r
\r
- Qh = EhcCreateQh (Ehc, &Ep);\r
+ Qh = EhcCreateQh (Ehc, &Ep);\r
\r
if (Qh == NULL) {\r
return EFI_OUT_OF_RESOURCES;\r
return EFI_SUCCESS;\r
}\r
\r
-\r
/**\r
Initialize the schedule data structure such as frame list.\r
\r
**/\r
EFI_STATUS\r
EhcInitSched (\r
- IN USB2_HC_DEV *Ehc\r
+ IN USB2_HC_DEV *Ehc\r
)\r
{\r
EFI_PCI_IO_PROTOCOL *PciIo;\r
return EFI_OUT_OF_RESOURCES;\r
}\r
\r
- Ehc->PeriodFrame = Buf;\r
- Ehc->PeriodFrameMap = Map;\r
+ Ehc->PeriodFrame = Buf;\r
+ Ehc->PeriodFrameMap = Map;\r
\r
//\r
// Program the FRAMELISTBASE register with the low 32 bit addr\r
//\r
// Initialize the frame list entries then set the registers\r
//\r
- Ehc->PeriodFrameHost = AllocateZeroPool (EHC_FRAME_LEN * sizeof (UINTN));\r
+ Ehc->PeriodFrameHost = AllocateZeroPool (EHC_FRAME_LEN * sizeof (UINTN));\r
if (Ehc->PeriodFrameHost == NULL) {\r
Status = EFI_OUT_OF_RESOURCES;\r
goto ErrorExit;\r
}\r
\r
- PciAddr = UsbHcGetPciAddressForHostMem (Ehc->MemPool, Ehc->PeriodOne, sizeof (EHC_QH));\r
+ PciAddr = UsbHcGetPciAddressForHostMem (Ehc->MemPool, Ehc->PeriodOne, sizeof (EHC_QH));\r
\r
for (Index = 0; Index < EHC_FRAME_LEN; Index++) {\r
//\r
return Status;\r
}\r
\r
-\r
/**\r
Free the schedule data. It may be partially initialized.\r
\r
**/\r
VOID\r
EhcFreeSched (\r
- IN USB2_HC_DEV *Ehc\r
+ IN USB2_HC_DEV *Ehc\r
)\r
{\r
- EFI_PCI_IO_PROTOCOL *PciIo;\r
+ EFI_PCI_IO_PROTOCOL *PciIo;\r
\r
EhcWriteOpReg (Ehc, EHC_FRAME_BASE_OFFSET, 0);\r
EhcWriteOpReg (Ehc, EHC_ASYNC_HEAD_OFFSET, 0);\r
}\r
}\r
\r
-\r
/**\r
Link the queue head to the asynchronous schedule list.\r
UEFI only supports one CTRL/BULK transfer at a time\r
**/\r
VOID\r
EhcLinkQhToAsync (\r
- IN USB2_HC_DEV *Ehc,\r
- IN EHC_QH *Qh\r
+ IN USB2_HC_DEV *Ehc,\r
+ IN EHC_QH *Qh\r
)\r
{\r
- EHC_QH *Head;\r
- EFI_PHYSICAL_ADDRESS PciAddr;\r
+ EHC_QH *Head;\r
+ EFI_PHYSICAL_ADDRESS PciAddr;\r
\r
//\r
// Append the queue head after the reclaim header, then\r
// fix the hardware visiable parts (EHCI R1.0 page 72).\r
// ReclaimHead is always linked to the EHCI's AsynListAddr.\r
//\r
- Head = Ehc->ReclaimHead;\r
+ Head = Ehc->ReclaimHead;\r
\r
- Qh->NextQh = Head->NextQh;\r
- Head->NextQh = Qh;\r
+ Qh->NextQh = Head->NextQh;\r
+ Head->NextQh = Qh;\r
\r
- PciAddr = UsbHcGetPciAddressForHostMem (Ehc->MemPool, Qh->NextQh, sizeof (EHC_QH));\r
- Qh->QhHw.HorizonLink = QH_LINK (PciAddr, EHC_TYPE_QH, FALSE);\r
- PciAddr = UsbHcGetPciAddressForHostMem (Ehc->MemPool, Head->NextQh, sizeof (EHC_QH));\r
- Head->QhHw.HorizonLink = QH_LINK (PciAddr, EHC_TYPE_QH, FALSE);\r
+ PciAddr = UsbHcGetPciAddressForHostMem (Ehc->MemPool, Qh->NextQh, sizeof (EHC_QH));\r
+ Qh->QhHw.HorizonLink = QH_LINK (PciAddr, EHC_TYPE_QH, FALSE);\r
+ PciAddr = UsbHcGetPciAddressForHostMem (Ehc->MemPool, Head->NextQh, sizeof (EHC_QH));\r
+ Head->QhHw.HorizonLink = QH_LINK (PciAddr, EHC_TYPE_QH, FALSE);\r
}\r
\r
-\r
/**\r
Unlink a queue head from the asynchronous schedule list.\r
Need to synchronize with hardware.\r
**/\r
VOID\r
EhcUnlinkQhFromAsync (\r
- IN USB2_HC_DEV *Ehc,\r
- IN EHC_QH *Qh\r
+ IN USB2_HC_DEV *Ehc,\r
+ IN EHC_QH *Qh\r
)\r
{\r
- EHC_QH *Head;\r
- EFI_STATUS Status;\r
- EFI_PHYSICAL_ADDRESS PciAddr;\r
+ EHC_QH *Head;\r
+ EFI_STATUS Status;\r
+ EFI_PHYSICAL_ADDRESS PciAddr;\r
\r
ASSERT (Ehc->ReclaimHead->NextQh == Qh);\r
\r
// visiable part: Only need to loopback the ReclaimHead. The Qh\r
// is pointing to ReclaimHead (which is staill in the list).\r
//\r
- Head = Ehc->ReclaimHead;\r
+ Head = Ehc->ReclaimHead;\r
\r
- Head->NextQh = Qh->NextQh;\r
- Qh->NextQh = NULL;\r
+ Head->NextQh = Qh->NextQh;\r
+ Qh->NextQh = NULL;\r
\r
- PciAddr = UsbHcGetPciAddressForHostMem (Ehc->MemPool, Head->NextQh, sizeof (EHC_QH));\r
- Head->QhHw.HorizonLink = QH_LINK (PciAddr, EHC_TYPE_QH, FALSE);\r
+ PciAddr = UsbHcGetPciAddressForHostMem (Ehc->MemPool, Head->NextQh, sizeof (EHC_QH));\r
+ Head->QhHw.HorizonLink = QH_LINK (PciAddr, EHC_TYPE_QH, FALSE);\r
\r
//\r
// Set and wait the door bell to synchronize with the hardware\r
}\r
}\r
\r
-\r
/**\r
Link a queue head for interrupt transfer to the periodic\r
schedule frame list. This code is very much the same as\r
**/\r
VOID\r
EhcLinkQhToPeriod (\r
- IN USB2_HC_DEV *Ehc,\r
- IN EHC_QH *Qh\r
+ IN USB2_HC_DEV *Ehc,\r
+ IN EHC_QH *Qh\r
)\r
{\r
- UINTN Index;\r
- EHC_QH *Prev;\r
- EHC_QH *Next;\r
- EFI_PHYSICAL_ADDRESS PciAddr;\r
+ UINTN Index;\r
+ EHC_QH *Prev;\r
+ EHC_QH *Next;\r
+ EFI_PHYSICAL_ADDRESS PciAddr;\r
\r
for (Index = 0; Index < EHC_FRAME_LEN; Index += Qh->Interval) {\r
//\r
// First QH can't be NULL because we always keep PeriodOne\r
// heads on the frame list\r
//\r
- ASSERT (!EHC_LINK_TERMINATED (((UINT32*)Ehc->PeriodFrame)[Index]));\r
- Next = (EHC_QH*)((UINTN*)Ehc->PeriodFrameHost)[Index];\r
- Prev = NULL;\r
+ ASSERT (!EHC_LINK_TERMINATED (((UINT32 *)Ehc->PeriodFrame)[Index]));\r
+ Next = (EHC_QH *)((UINTN *)Ehc->PeriodFrameHost)[Index];\r
+ Prev = NULL;\r
\r
//\r
// Now, insert the queue head (Qh) into this frame:\r
// Then, insert the Qh between then\r
//\r
while (Next->Interval > Qh->Interval) {\r
- Prev = Next;\r
- Next = Next->NextQh;\r
+ Prev = Next;\r
+ Next = Next->NextQh;\r
}\r
\r
ASSERT (Next != NULL);\r
//\r
ASSERT ((Index == 0) && (Qh->NextQh == NULL));\r
\r
- Prev = Next;\r
- Next = Next->NextQh;\r
+ Prev = Next;\r
+ Next = Next->NextQh;\r
\r
- Qh->NextQh = Next;\r
- Prev->NextQh = Qh;\r
+ Qh->NextQh = Next;\r
+ Prev->NextQh = Qh;\r
\r
- Qh->QhHw.HorizonLink = Prev->QhHw.HorizonLink;\r
- PciAddr = UsbHcGetPciAddressForHostMem (Ehc->MemPool, Qh, sizeof (EHC_QH));\r
- Prev->QhHw.HorizonLink = QH_LINK (PciAddr, EHC_TYPE_QH, FALSE);\r
+ Qh->QhHw.HorizonLink = Prev->QhHw.HorizonLink;\r
+ PciAddr = UsbHcGetPciAddressForHostMem (Ehc->MemPool, Qh, sizeof (EHC_QH));\r
+ Prev->QhHw.HorizonLink = QH_LINK (PciAddr, EHC_TYPE_QH, FALSE);\r
break;\r
}\r
\r
// guarranted by 2^n polling interval.\r
//\r
if (Qh->NextQh == NULL) {\r
- Qh->NextQh = Next;\r
- PciAddr = UsbHcGetPciAddressForHostMem (Ehc->MemPool, Next, sizeof (EHC_QH));\r
- Qh->QhHw.HorizonLink = QH_LINK (PciAddr, EHC_TYPE_QH, FALSE);\r
+ Qh->NextQh = Next;\r
+ PciAddr = UsbHcGetPciAddressForHostMem (Ehc->MemPool, Next, sizeof (EHC_QH));\r
+ Qh->QhHw.HorizonLink = QH_LINK (PciAddr, EHC_TYPE_QH, FALSE);\r
}\r
\r
PciAddr = UsbHcGetPciAddressForHostMem (Ehc->MemPool, Qh, sizeof (EHC_QH));\r
\r
if (Prev == NULL) {\r
- ((UINT32*)Ehc->PeriodFrame)[Index] = QH_LINK (PciAddr, EHC_TYPE_QH, FALSE);\r
- ((UINTN*)Ehc->PeriodFrameHost)[Index] = (UINTN)Qh;\r
+ ((UINT32 *)Ehc->PeriodFrame)[Index] = QH_LINK (PciAddr, EHC_TYPE_QH, FALSE);\r
+ ((UINTN *)Ehc->PeriodFrameHost)[Index] = (UINTN)Qh;\r
} else {\r
- Prev->NextQh = Qh;\r
- Prev->QhHw.HorizonLink = QH_LINK (PciAddr, EHC_TYPE_QH, FALSE);\r
+ Prev->NextQh = Qh;\r
+ Prev->QhHw.HorizonLink = QH_LINK (PciAddr, EHC_TYPE_QH, FALSE);\r
}\r
}\r
}\r
\r
-\r
/**\r
Unlink an interrupt queue head from the periodic\r
schedule frame list.\r
**/\r
VOID\r
EhcUnlinkQhFromPeriod (\r
- IN USB2_HC_DEV *Ehc,\r
- IN EHC_QH *Qh\r
+ IN USB2_HC_DEV *Ehc,\r
+ IN EHC_QH *Qh\r
)\r
{\r
- UINTN Index;\r
- EHC_QH *Prev;\r
- EHC_QH *This;\r
+ UINTN Index;\r
+ EHC_QH *Prev;\r
+ EHC_QH *This;\r
\r
for (Index = 0; Index < EHC_FRAME_LEN; Index += Qh->Interval) {\r
//\r
// Frame link can't be NULL because we always keep PeroidOne\r
// on the frame list\r
//\r
- ASSERT (!EHC_LINK_TERMINATED (((UINT32*)Ehc->PeriodFrame)[Index]));\r
- This = (EHC_QH*)((UINTN*)Ehc->PeriodFrameHost)[Index];\r
- Prev = NULL;\r
+ ASSERT (!EHC_LINK_TERMINATED (((UINT32 *)Ehc->PeriodFrame)[Index]));\r
+ This = (EHC_QH *)((UINTN *)Ehc->PeriodFrameHost)[Index];\r
+ Prev = NULL;\r
\r
//\r
// Walk through the frame's QH list to find the\r
// queue head to remove\r
//\r
while ((This != NULL) && (This != Qh)) {\r
- Prev = This;\r
- This = This->NextQh;\r
+ Prev = This;\r
+ This = This->NextQh;\r
}\r
\r
//\r
//\r
// Qh is the first entry in the frame\r
//\r
- ((UINT32*)Ehc->PeriodFrame)[Index] = Qh->QhHw.HorizonLink;\r
- ((UINTN*)Ehc->PeriodFrameHost)[Index] = (UINTN)Qh->NextQh;\r
+ ((UINT32 *)Ehc->PeriodFrame)[Index] = Qh->QhHw.HorizonLink;\r
+ ((UINTN *)Ehc->PeriodFrameHost)[Index] = (UINTN)Qh->NextQh;\r
} else {\r
- Prev->NextQh = Qh->NextQh;\r
- Prev->QhHw.HorizonLink = Qh->QhHw.HorizonLink;\r
+ Prev->NextQh = Qh->NextQh;\r
+ Prev->QhHw.HorizonLink = Qh->QhHw.HorizonLink;\r
}\r
}\r
}\r
\r
-\r
/**\r
Check the URB's execution result and update the URB's\r
result accordingly.\r
**/\r
BOOLEAN\r
EhcCheckUrbResult (\r
- IN USB2_HC_DEV *Ehc,\r
- IN URB *Urb\r
+ IN USB2_HC_DEV *Ehc,\r
+ IN URB *Urb\r
)\r
{\r
- LIST_ENTRY *Entry;\r
- EHC_QTD *Qtd;\r
- QTD_HW *QtdHw;\r
- UINT8 State;\r
- BOOLEAN Finished;\r
- EFI_PHYSICAL_ADDRESS PciAddr;\r
+ LIST_ENTRY *Entry;\r
+ EHC_QTD *Qtd;\r
+ QTD_HW *QtdHw;\r
+ UINT8 State;\r
+ BOOLEAN Finished;\r
+ EFI_PHYSICAL_ADDRESS PciAddr;\r
\r
ASSERT ((Ehc != NULL) && (Urb != NULL) && (Urb->Qh != NULL));\r
\r
- Finished = TRUE;\r
- Urb->Completed = 0;\r
+ Finished = TRUE;\r
+ Urb->Completed = 0;\r
\r
- Urb->Result = EFI_USB_NOERROR;\r
+ Urb->Result = EFI_USB_NOERROR;\r
\r
if (EhcIsHalt (Ehc) || EhcIsSysError (Ehc)) {\r
Urb->Result |= EFI_USB_ERR_SYSTEM;\r
BASE_LIST_FOR_EACH (Entry, &Urb->Qh->Qtds) {\r
Qtd = EFI_LIST_CONTAINER (Entry, EHC_QTD, QtdList);\r
QtdHw = &Qtd->QtdHw;\r
- State = (UINT8) QtdHw->Status;\r
+ State = (UINT8)QtdHw->Status;\r
\r
if (EHC_BIT_IS_SET (State, QTD_STAT_HALTED)) {\r
//\r
\r
Finished = TRUE;\r
goto ON_EXIT;\r
-\r
} else if (EHC_BIT_IS_SET (State, QTD_STAT_ACTIVE)) {\r
//\r
// The QTD is still active, no need to check furthur.\r
\r
Finished = FALSE;\r
goto ON_EXIT;\r
-\r
} else {\r
//\r
// This QTD is finished OK or met short packet read. Update the\r
// NOTICE: don't move DT update before the loop, otherwise there is\r
// a race condition that DT is wrong.\r
//\r
- Urb->DataToggle = (UINT8) Urb->Qh->QhHw.DataToggle;\r
+ Urb->DataToggle = (UINT8)Urb->Qh->QhHw.DataToggle;\r
\r
return Finished;\r
}\r
\r
-\r
/**\r
Execute the transfer by polling the URB. This is a synchronous operation.\r
\r
**/\r
EFI_STATUS\r
EhcExecTransfer (\r
- IN USB2_HC_DEV *Ehc,\r
- IN URB *Urb,\r
- IN UINTN TimeOut\r
+ IN USB2_HC_DEV *Ehc,\r
+ IN URB *Urb,\r
+ IN UINTN TimeOut\r
)\r
{\r
- EFI_STATUS Status;\r
- UINTN Index;\r
- UINTN Loop;\r
- BOOLEAN Finished;\r
- BOOLEAN InfiniteLoop;\r
+ EFI_STATUS Status;\r
+ UINTN Index;\r
+ UINTN Loop;\r
+ BOOLEAN Finished;\r
+ BOOLEAN InfiniteLoop;\r
\r
Status = EFI_SUCCESS;\r
Loop = TimeOut * EHC_1_MILLISECOND;\r
EhcDumpQh (Urb->Qh, NULL, FALSE);\r
\r
Status = EFI_TIMEOUT;\r
-\r
} else if (Urb->Result != EFI_USB_NOERROR) {\r
DEBUG ((DEBUG_ERROR, "EhcExecTransfer: transfer failed with %x\n", Urb->Result));\r
EhcDumpQh (Urb->Qh, NULL, FALSE);\r
return Status;\r
}\r
\r
-\r
/**\r
Delete a single asynchronous interrupt transfer for\r
the device and endpoint.\r
**/\r
EFI_STATUS\r
EhciDelAsyncIntTransfer (\r
- IN USB2_HC_DEV *Ehc,\r
- IN UINT8 DevAddr,\r
- IN UINT8 EpNum,\r
- OUT UINT8 *DataToggle\r
+ IN USB2_HC_DEV *Ehc,\r
+ IN UINT8 DevAddr,\r
+ IN UINT8 EpNum,\r
+ OUT UINT8 *DataToggle\r
)\r
{\r
LIST_ENTRY *Entry;\r
Urb = EFI_LIST_CONTAINER (Entry, URB, UrbList);\r
\r
if ((Urb->Ep.DevAddr == DevAddr) && (Urb->Ep.EpAddr == EpNum) &&\r
- (Urb->Ep.Direction == Direction)) {\r
+ (Urb->Ep.Direction == Direction))\r
+ {\r
//\r
// Check the URB status to retrieve the next data toggle\r
// from the associated queue head.\r
return EFI_NOT_FOUND;\r
}\r
\r
-\r
/**\r
Remove all the asynchronous interrutp transfers.\r
\r
**/\r
VOID\r
EhciDelAllAsyncIntTransfers (\r
- IN USB2_HC_DEV *Ehc\r
+ IN USB2_HC_DEV *Ehc\r
)\r
{\r
- LIST_ENTRY *Entry;\r
- LIST_ENTRY *Next;\r
- URB *Urb;\r
+ LIST_ENTRY *Entry;\r
+ LIST_ENTRY *Next;\r
+ URB *Urb;\r
\r
BASE_LIST_FOR_EACH_SAFE (Entry, Next, &Ehc->AsyncIntTransfers) {\r
Urb = EFI_LIST_CONTAINER (Entry, URB, UrbList);\r
**/\r
URB *\r
EhciInsertAsyncIntTransfer (\r
- IN USB2_HC_DEV *Ehc,\r
- IN UINT8 DevAddr,\r
- IN UINT8 EpAddr,\r
- IN UINT8 DevSpeed,\r
- IN UINT8 Toggle,\r
- IN UINTN MaxPacket,\r
- IN EFI_USB2_HC_TRANSACTION_TRANSLATOR *Hub,\r
- IN UINTN DataLen,\r
- IN EFI_ASYNC_USB_TRANSFER_CALLBACK Callback,\r
- IN VOID *Context,\r
- IN UINTN Interval\r
+ IN USB2_HC_DEV *Ehc,\r
+ IN UINT8 DevAddr,\r
+ IN UINT8 EpAddr,\r
+ IN UINT8 DevSpeed,\r
+ IN UINT8 Toggle,\r
+ IN UINTN MaxPacket,\r
+ IN EFI_USB2_HC_TRANSACTION_TRANSLATOR *Hub,\r
+ IN UINTN DataLen,\r
+ IN EFI_ASYNC_USB_TRANSFER_CALLBACK Callback,\r
+ IN VOID *Context,\r
+ IN UINTN Interval\r
)\r
{\r
- VOID *Data;\r
- URB *Urb;\r
+ VOID *Data;\r
+ URB *Urb;\r
\r
Data = AllocatePool (DataLen);\r
\r
**/\r
EFI_STATUS\r
EhcFlushAsyncIntMap (\r
- IN USB2_HC_DEV *Ehc,\r
- IN URB *Urb\r
+ IN USB2_HC_DEV *Ehc,\r
+ IN URB *Urb\r
)\r
{\r
- EFI_STATUS Status;\r
- EFI_PHYSICAL_ADDRESS PhyAddr;\r
- EFI_PCI_IO_PROTOCOL_OPERATION MapOp;\r
- EFI_PCI_IO_PROTOCOL *PciIo;\r
- UINTN Len;\r
- VOID *Map;\r
+ EFI_STATUS Status;\r
+ EFI_PHYSICAL_ADDRESS PhyAddr;\r
+ EFI_PCI_IO_PROTOCOL_OPERATION MapOp;\r
+ EFI_PCI_IO_PROTOCOL *PciIo;\r
+ UINTN Len;\r
+ VOID *Map;\r
\r
PciIo = Ehc->PciIo;\r
Len = Urb->DataLen;\r
goto ON_ERROR;\r
}\r
\r
- Urb->DataPhy = (VOID *) ((UINTN) PhyAddr);\r
- Urb->DataMap = Map;\r
+ Urb->DataPhy = (VOID *)((UINTN)PhyAddr);\r
+ Urb->DataMap = Map;\r
return EFI_SUCCESS;\r
\r
ON_ERROR:\r
return EFI_DEVICE_ERROR;\r
}\r
\r
-\r
/**\r
Update the queue head for next round of asynchronous transfer.\r
\r
**/\r
VOID\r
EhcUpdateAsyncRequest (\r
- IN USB2_HC_DEV *Ehc,\r
- IN URB *Urb\r
+ IN USB2_HC_DEV *Ehc,\r
+ IN URB *Urb\r
)\r
{\r
- LIST_ENTRY *Entry;\r
- EHC_QTD *FirstQtd;\r
- QH_HW *QhHw;\r
- EHC_QTD *Qtd;\r
- QTD_HW *QtdHw;\r
- UINTN Index;\r
- EFI_PHYSICAL_ADDRESS PciAddr;\r
+ LIST_ENTRY *Entry;\r
+ EHC_QTD *FirstQtd;\r
+ QH_HW *QhHw;\r
+ EHC_QTD *Qtd;\r
+ QTD_HW *QtdHw;\r
+ UINTN Index;\r
+ EFI_PHYSICAL_ADDRESS PciAddr;\r
\r
Qtd = NULL;\r
\r
QtdHw->Status = QTD_STAT_ACTIVE;\r
QtdHw->ErrCnt = QTD_MAX_ERR;\r
QtdHw->CurPage = 0;\r
- QtdHw->TotalBytes = (UINT32) Qtd->DataLen;\r
+ QtdHw->TotalBytes = (UINT32)Qtd->DataLen;\r
//\r
// calculate physical address by offset.\r
//\r
- PciAddr = (UINTN)Urb->DataPhy + ((UINTN)Qtd->Data - (UINTN)Urb->Data);\r
- QtdHw->Page[0] = EHC_LOW_32BIT (PciAddr);\r
- QtdHw->PageHigh[0]= EHC_HIGH_32BIT (PciAddr);\r
+ PciAddr = (UINTN)Urb->DataPhy + ((UINTN)Qtd->Data - (UINTN)Urb->Data);\r
+ QtdHw->Page[0] = EHC_LOW_32BIT (PciAddr);\r
+ QtdHw->PageHigh[0] = EHC_HIGH_32BIT (PciAddr);\r
}\r
\r
//\r
// zero out the overlay area and set NextQtd to the first\r
// QTD. DateToggle bit is left untouched.\r
//\r
- QhHw = &Urb->Qh->QhHw;\r
- QhHw->CurQtd = QTD_LINK (0, TRUE);\r
- QhHw->AltQtd = 0;\r
+ QhHw = &Urb->Qh->QhHw;\r
+ QhHw->CurQtd = QTD_LINK (0, TRUE);\r
+ QhHw->AltQtd = 0;\r
\r
- QhHw->Status = 0;\r
- QhHw->Pid = 0;\r
- QhHw->ErrCnt = 0;\r
- QhHw->CurPage = 0;\r
- QhHw->Ioc = 0;\r
- QhHw->TotalBytes = 0;\r
+ QhHw->Status = 0;\r
+ QhHw->Pid = 0;\r
+ QhHw->ErrCnt = 0;\r
+ QhHw->CurPage = 0;\r
+ QhHw->Ioc = 0;\r
+ QhHw->TotalBytes = 0;\r
\r
for (Index = 0; Index < 5; Index++) {\r
QhHw->Page[Index] = 0;\r
QhHw->PageHigh[Index] = 0;\r
}\r
\r
- PciAddr = UsbHcGetPciAddressForHostMem (Ehc->MemPool, FirstQtd, sizeof (EHC_QTD));\r
+ PciAddr = UsbHcGetPciAddressForHostMem (Ehc->MemPool, FirstQtd, sizeof (EHC_QTD));\r
QhHw->NextQtd = QTD_LINK (PciAddr, FALSE);\r
}\r
\r
- return ;\r
+ return;\r
}\r
\r
-\r
/**\r
Interrupt transfer periodic check handler.\r
\r
VOID\r
EFIAPI\r
EhcMonitorAsyncRequests (\r
- IN EFI_EVENT Event,\r
- IN VOID *Context\r
+ IN EFI_EVENT Event,\r
+ IN VOID *Context\r
)\r
{\r
- USB2_HC_DEV *Ehc;\r
- EFI_TPL OldTpl;\r
- LIST_ENTRY *Entry;\r
- LIST_ENTRY *Next;\r
- BOOLEAN Finished;\r
- UINT8 *ProcBuf;\r
- URB *Urb;\r
- EFI_STATUS Status;\r
-\r
- OldTpl = gBS->RaiseTPL (EHC_TPL);\r
- Ehc = (USB2_HC_DEV *) Context;\r
+ USB2_HC_DEV *Ehc;\r
+ EFI_TPL OldTpl;\r
+ LIST_ENTRY *Entry;\r
+ LIST_ENTRY *Next;\r
+ BOOLEAN Finished;\r
+ UINT8 *ProcBuf;\r
+ URB *Urb;\r
+ EFI_STATUS Status;\r
+\r
+ OldTpl = gBS->RaiseTPL (EHC_TPL);\r
+ Ehc = (USB2_HC_DEV *)Context;\r
\r
BASE_LIST_FOR_EACH_SAFE (Entry, Next, &Ehc->AsyncIntTransfers) {\r
Urb = EFI_LIST_CONTAINER (Entry, URB, UrbList);\r
// his callback. Some drivers may has a lower TPL restriction.\r
//\r
gBS->RestoreTPL (OldTpl);\r
- (Urb->Callback) (ProcBuf, Urb->Completed, Urb->Context, Urb->Result);\r
+ (Urb->Callback)(ProcBuf, Urb->Completed, Urb->Context, Urb->Result);\r
OldTpl = gBS->RaiseTPL (EHC_TPL);\r
}\r
\r
projects / mirror_edk2.git / blobdiff