// to the UEFI protocol's port state (change).\r
//\r
USB_PORT_STATE_MAP mUsbPortStateMap[] = {\r
- {PORTSC_CONN, USB_PORT_STAT_CONNECTION},\r
- {PORTSC_ENABLED, USB_PORT_STAT_ENABLE},\r
- {PORTSC_SUSPEND, USB_PORT_STAT_SUSPEND},\r
- {PORTSC_OVERCUR, USB_PORT_STAT_OVERCURRENT},\r
- {PORTSC_RESET, USB_PORT_STAT_RESET},\r
- {PORTSC_POWER, USB_PORT_STAT_POWER},\r
- {PORTSC_OWNER, USB_PORT_STAT_OWNER}\r
+ { PORTSC_CONN, USB_PORT_STAT_CONNECTION },\r
+ { PORTSC_ENABLED, USB_PORT_STAT_ENABLE },\r
+ { PORTSC_SUSPEND, USB_PORT_STAT_SUSPEND },\r
+ { PORTSC_OVERCUR, USB_PORT_STAT_OVERCURRENT },\r
+ { PORTSC_RESET, USB_PORT_STAT_RESET },\r
+ { PORTSC_POWER, USB_PORT_STAT_POWER },\r
+ { PORTSC_OWNER, USB_PORT_STAT_OWNER }\r
};\r
\r
USB_PORT_STATE_MAP mUsbPortChangeMap[] = {\r
- {PORTSC_CONN_CHANGE, USB_PORT_STAT_C_CONNECTION},\r
- {PORTSC_ENABLE_CHANGE, USB_PORT_STAT_C_ENABLE},\r
- {PORTSC_OVERCUR_CHANGE, USB_PORT_STAT_C_OVERCURRENT}\r
+ { PORTSC_CONN_CHANGE, USB_PORT_STAT_C_CONNECTION },\r
+ { PORTSC_ENABLE_CHANGE, USB_PORT_STAT_C_ENABLE },\r
+ { PORTSC_OVERCUR_CHANGE, USB_PORT_STAT_C_OVERCURRENT }\r
};\r
\r
/**\r
**/\r
UINT32\r
EhcReadOpReg (\r
- IN PEI_USB2_HC_DEV *Ehc,\r
- IN UINT32 Offset\r
+ IN PEI_USB2_HC_DEV *Ehc,\r
+ IN UINT32 Offset\r
)\r
{\r
- UINT32 Data;\r
+ UINT32 Data;\r
\r
ASSERT (Ehc->CapLen != 0);\r
\r
**/\r
VOID\r
EhcWriteOpReg (\r
- IN PEI_USB2_HC_DEV *Ehc,\r
- IN UINT32 Offset,\r
- IN UINT32 Data\r
+ IN PEI_USB2_HC_DEV *Ehc,\r
+ IN UINT32 Offset,\r
+ IN UINT32 Data\r
)\r
{\r
-\r
ASSERT (Ehc->CapLen != 0);\r
\r
- MmioWrite32(Ehc->UsbHostControllerBaseAddress + Ehc->CapLen + Offset, Data);\r
-\r
+ MmioWrite32 (Ehc->UsbHostControllerBaseAddress + Ehc->CapLen + Offset, Data);\r
}\r
\r
/**\r
**/\r
VOID\r
EhcSetOpRegBit (\r
- IN PEI_USB2_HC_DEV *Ehc,\r
- IN UINT32 Offset,\r
- IN UINT32 Bit\r
+ IN PEI_USB2_HC_DEV *Ehc,\r
+ IN UINT32 Offset,\r
+ IN UINT32 Bit\r
)\r
{\r
- UINT32 Data;\r
+ UINT32 Data;\r
\r
Data = EhcReadOpReg (Ehc, Offset);\r
Data |= Bit;\r
**/\r
VOID\r
EhcClearOpRegBit (\r
- IN PEI_USB2_HC_DEV *Ehc,\r
- IN UINT32 Offset,\r
- IN UINT32 Bit\r
+ IN PEI_USB2_HC_DEV *Ehc,\r
+ IN UINT32 Offset,\r
+ IN UINT32 Bit\r
)\r
{\r
- UINT32 Data;\r
+ UINT32 Data;\r
\r
Data = EhcReadOpReg (Ehc, Offset);\r
Data &= ~Bit;\r
**/\r
EFI_STATUS\r
EhcWaitOpRegBit (\r
- IN PEI_USB2_HC_DEV *Ehc,\r
- IN UINT32 Offset,\r
- IN UINT32 Bit,\r
- IN BOOLEAN WaitToSet,\r
- IN UINT32 Timeout\r
+ IN PEI_USB2_HC_DEV *Ehc,\r
+ IN UINT32 Offset,\r
+ IN UINT32 Bit,\r
+ IN BOOLEAN WaitToSet,\r
+ IN UINT32 Timeout\r
)\r
{\r
- UINT32 Index;\r
+ UINT32 Index;\r
\r
for (Index = 0; Index < Timeout / EHC_SYNC_POLL_INTERVAL + 1; Index++) {\r
if (EHC_REG_BIT_IS_SET (Ehc, Offset, Bit) == WaitToSet) {\r
**/\r
UINT32\r
EhcReadCapRegister (\r
- IN PEI_USB2_HC_DEV *Ehc,\r
- IN UINT32 Offset\r
+ IN PEI_USB2_HC_DEV *Ehc,\r
+ IN UINT32 Offset\r
)\r
{\r
- UINT32 Data;\r
+ UINT32 Data;\r
\r
- Data = MmioRead32(Ehc->UsbHostControllerBaseAddress + Offset);\r
+ Data = MmioRead32 (Ehc->UsbHostControllerBaseAddress + Offset);\r
\r
return Data;\r
}\r
**/\r
EFI_STATUS\r
EhcSetAndWaitDoorBell (\r
- IN PEI_USB2_HC_DEV *Ehc,\r
- IN UINT32 Timeout\r
+ IN PEI_USB2_HC_DEV *Ehc,\r
+ IN UINT32 Timeout\r
)\r
{\r
- EFI_STATUS Status;\r
- UINT32 Data;\r
+ EFI_STATUS Status;\r
+ UINT32 Data;\r
\r
EhcSetOpRegBit (Ehc, EHC_USBCMD_OFFSET, USBCMD_IAAD);\r
\r
**/\r
VOID\r
EhcAckAllInterrupt (\r
- IN PEI_USB2_HC_DEV *Ehc\r
+ IN PEI_USB2_HC_DEV *Ehc\r
)\r
{\r
EhcWriteOpReg (Ehc, EHC_USBSTS_OFFSET, USBSTS_INTACK_MASK);\r
**/\r
EFI_STATUS\r
EhcEnablePeriodSchd (\r
- IN PEI_USB2_HC_DEV *Ehc,\r
- IN UINT32 Timeout\r
+ IN PEI_USB2_HC_DEV *Ehc,\r
+ IN UINT32 Timeout\r
)\r
{\r
- EFI_STATUS Status;\r
+ EFI_STATUS Status;\r
\r
EhcSetOpRegBit (Ehc, EHC_USBCMD_OFFSET, USBCMD_ENABLE_PERIOD);\r
\r
**/\r
EFI_STATUS\r
EhcEnableAsyncSchd (\r
- IN PEI_USB2_HC_DEV *Ehc,\r
- IN UINT32 Timeout\r
+ IN PEI_USB2_HC_DEV *Ehc,\r
+ IN UINT32 Timeout\r
)\r
{\r
- EFI_STATUS Status;\r
+ EFI_STATUS Status;\r
\r
EhcSetOpRegBit (Ehc, EHC_USBCMD_OFFSET, USBCMD_ENABLE_ASYNC);\r
\r
**/\r
BOOLEAN\r
EhcIsHalt (\r
- IN PEI_USB2_HC_DEV *Ehc\r
+ IN PEI_USB2_HC_DEV *Ehc\r
)\r
{\r
return EHC_REG_BIT_IS_SET (Ehc, EHC_USBSTS_OFFSET, USBSTS_HALT);\r
**/\r
BOOLEAN\r
EhcIsSysError (\r
- IN PEI_USB2_HC_DEV *Ehc\r
+ IN PEI_USB2_HC_DEV *Ehc\r
)\r
{\r
return EHC_REG_BIT_IS_SET (Ehc, EHC_USBSTS_OFFSET, USBSTS_SYS_ERROR);\r
**/\r
EFI_STATUS\r
EhcResetHC (\r
- IN PEI_USB2_HC_DEV *Ehc,\r
- IN UINT32 Timeout\r
+ IN PEI_USB2_HC_DEV *Ehc,\r
+ IN UINT32 Timeout\r
)\r
{\r
- EFI_STATUS Status;\r
+ EFI_STATUS Status;\r
\r
//\r
// Host can only be reset when it is halt. If not so, halt it\r
**/\r
EFI_STATUS\r
EhcHaltHC (\r
- IN PEI_USB2_HC_DEV *Ehc,\r
- IN UINT32 Timeout\r
+ IN PEI_USB2_HC_DEV *Ehc,\r
+ IN UINT32 Timeout\r
)\r
{\r
- EFI_STATUS Status;\r
+ EFI_STATUS Status;\r
\r
EhcClearOpRegBit (Ehc, EHC_USBCMD_OFFSET, USBCMD_RUN);\r
Status = EhcWaitOpRegBit (Ehc, EHC_USBSTS_OFFSET, USBSTS_HALT, TRUE, Timeout);\r
**/\r
EFI_STATUS\r
EhcRunHC (\r
- IN PEI_USB2_HC_DEV *Ehc,\r
- IN UINT32 Timeout\r
+ IN PEI_USB2_HC_DEV *Ehc,\r
+ IN UINT32 Timeout\r
)\r
{\r
- EFI_STATUS Status;\r
+ EFI_STATUS Status;\r
\r
EhcSetOpRegBit (Ehc, EHC_USBCMD_OFFSET, USBCMD_RUN);\r
Status = EhcWaitOpRegBit (Ehc, EHC_USBSTS_OFFSET, USBSTS_HALT, FALSE, Timeout);\r
**/\r
VOID\r
EhcPowerOnAllPorts (\r
- IN PEI_USB2_HC_DEV *Ehc\r
+ IN PEI_USB2_HC_DEV *Ehc\r
)\r
{\r
- UINT8 PortNumber;\r
- UINT8 Index;\r
- UINT32 RegVal;\r
+ UINT8 PortNumber;\r
+ UINT8 Index;\r
+ UINT32 RegVal;\r
\r
PortNumber = (UINT8)(Ehc->HcStructParams & HCSP_NPORTS);\r
for (Index = 0; Index < PortNumber; Index++) {\r
// Do not clear port status bits on initialization. Otherwise devices will\r
// not enumerate properly at startup.\r
//\r
- RegVal = EhcReadOpReg(Ehc, EHC_PORT_STAT_OFFSET + 4 * Index);\r
+ RegVal = EhcReadOpReg (Ehc, EHC_PORT_STAT_OFFSET + 4 * Index);\r
RegVal &= ~PORTSC_CHANGE_MASK;\r
RegVal |= PORTSC_POWER;\r
EhcWriteOpReg (Ehc, EHC_PORT_STAT_OFFSET + 4 * Index, RegVal);\r
**/\r
EFI_STATUS\r
EhcInitHC (\r
- IN PEI_USB2_HC_DEV *Ehc\r
+ IN PEI_USB2_HC_DEV *Ehc\r
)\r
{\r
- EFI_STATUS Status;\r
- EFI_PHYSICAL_ADDRESS TempPtr;\r
- UINTN PageNumber;\r
+ EFI_STATUS Status;\r
+ EFI_PHYSICAL_ADDRESS TempPtr;\r
+ UINTN PageNumber;\r
\r
ASSERT (EhcIsHalt (Ehc));\r
\r
if (Ehc->PeriodFrame != NULL) {\r
EhcFreeSched (Ehc);\r
}\r
- PageNumber = sizeof(PEI_URB)/PAGESIZE +1;\r
- Status = PeiServicesAllocatePages (\r
- EfiBootServicesCode,\r
- PageNumber,\r
- &TempPtr\r
- );\r
- Ehc->Urb = (PEI_URB *) ((UINTN) TempPtr);\r
+\r
+ PageNumber = sizeof (PEI_URB)/PAGESIZE +1;\r
+ Status = PeiServicesAllocatePages (\r
+ EfiBootServicesCode,\r
+ PageNumber,\r
+ &TempPtr\r
+ );\r
+ Ehc->Urb = (PEI_URB *)((UINTN)TempPtr);\r
if (Ehc->Urb == NULL) {\r
return Status;\r
}\r
if (EFI_ERROR (Status)) {\r
return Status;\r
}\r
+\r
//\r
// 1. Program the CTRLDSSEGMENT register with the high 32 bit addr\r
//\r
OUT UINT32 *TransferResult\r
)\r
{\r
- PEI_USB2_HC_DEV *Ehc;\r
- PEI_URB *Urb;\r
- EFI_STATUS Status;\r
+ PEI_USB2_HC_DEV *Ehc;\r
+ PEI_URB *Urb;\r
+ EFI_STATUS Status;\r
\r
//\r
// Validate the parameters\r
//\r
if ((DataLength == NULL) || (*DataLength == 0) ||\r
- (Data == NULL) || (Data[0] == NULL) || (TransferResult == NULL)) {\r
+ (Data == NULL) || (Data[0] == NULL) || (TransferResult == NULL))\r
+ {\r
return EFI_INVALID_PARAMETER;\r
}\r
\r
\r
if ((DeviceSpeed == EFI_USB_SPEED_LOW) ||\r
((DeviceSpeed == EFI_USB_SPEED_FULL) && (MaximumPacketLength > 64)) ||\r
- ((EFI_USB_SPEED_HIGH == DeviceSpeed) && (MaximumPacketLength > 512))) {\r
+ ((EFI_USB_SPEED_HIGH == DeviceSpeed) && (MaximumPacketLength > 512)))\r
+ {\r
return EFI_INVALID_PARAMETER;\r
}\r
\r
- Ehc =PEI_RECOVERY_USB_EHC_DEV_FROM_EHCI_THIS(This);\r
+ Ehc = PEI_RECOVERY_USB_EHC_DEV_FROM_EHCI_THIS (This);\r
*TransferResult = EFI_USB_ERR_SYSTEM;\r
Status = EFI_DEVICE_ERROR;\r
\r
EFI_STATUS\r
EFIAPI\r
EhcGetRootHubPortNumber (\r
- IN EFI_PEI_SERVICES **PeiServices,\r
- IN PEI_USB2_HOST_CONTROLLER_PPI *This,\r
- OUT UINT8 *PortNumber\r
+ IN EFI_PEI_SERVICES **PeiServices,\r
+ IN PEI_USB2_HOST_CONTROLLER_PPI *This,\r
+ OUT UINT8 *PortNumber\r
)\r
{\r
+ PEI_USB2_HC_DEV *EhcDev;\r
\r
- PEI_USB2_HC_DEV *EhcDev;\r
EhcDev = PEI_RECOVERY_USB_EHC_DEV_FROM_EHCI_THIS (This);\r
\r
if (PortNumber == NULL) {\r
\r
*PortNumber = (UINT8)(EhcDev->HcStructParams & HCSP_NPORTS);\r
return EFI_SUCCESS;\r
-\r
}\r
\r
/**\r
EFI_STATUS\r
EFIAPI\r
EhcClearRootHubPortFeature (\r
- IN EFI_PEI_SERVICES **PeiServices,\r
- IN PEI_USB2_HOST_CONTROLLER_PPI *This,\r
- IN UINT8 PortNumber,\r
- IN EFI_USB_PORT_FEATURE PortFeature\r
+ IN EFI_PEI_SERVICES **PeiServices,\r
+ IN PEI_USB2_HOST_CONTROLLER_PPI *This,\r
+ IN UINT8 PortNumber,\r
+ IN EFI_USB_PORT_FEATURE PortFeature\r
)\r
{\r
- PEI_USB2_HC_DEV *Ehc;\r
- UINT32 Offset;\r
- UINT32 State;\r
- UINT32 TotalPort;\r
- EFI_STATUS Status;\r
+ PEI_USB2_HC_DEV *Ehc;\r
+ UINT32 Offset;\r
+ UINT32 State;\r
+ UINT32 TotalPort;\r
+ EFI_STATUS Status;\r
\r
- Ehc = PEI_RECOVERY_USB_EHC_DEV_FROM_EHCI_THIS (This);\r
- Status = EFI_SUCCESS;\r
+ Ehc = PEI_RECOVERY_USB_EHC_DEV_FROM_EHCI_THIS (This);\r
+ Status = EFI_SUCCESS;\r
\r
TotalPort = (Ehc->HcStructParams & HCSP_NPORTS);\r
\r
goto ON_EXIT;\r
}\r
\r
- Offset = EHC_PORT_STAT_OFFSET + (4 * PortNumber);\r
- State = EhcReadOpReg (Ehc, Offset);\r
+ Offset = EHC_PORT_STAT_OFFSET + (4 * PortNumber);\r
+ State = EhcReadOpReg (Ehc, Offset);\r
State &= ~PORTSC_CHANGE_MASK;\r
\r
switch (PortFeature) {\r
- case EfiUsbPortEnable:\r
- //\r
- // Clear PORT_ENABLE feature means disable port.\r
- //\r
- State &= ~PORTSC_ENABLED;\r
- EhcWriteOpReg (Ehc, Offset, State);\r
- break;\r
+ case EfiUsbPortEnable:\r
+ //\r
+ // Clear PORT_ENABLE feature means disable port.\r
+ //\r
+ State &= ~PORTSC_ENABLED;\r
+ EhcWriteOpReg (Ehc, Offset, State);\r
+ break;\r
\r
- case EfiUsbPortSuspend:\r
- //\r
- // A write of zero to this bit is ignored by the host\r
- // controller. The host controller will unconditionally\r
- // set this bit to a zero when:\r
- // 1. software sets the Forct Port Resume bit to a zero from a one.\r
- // 2. software sets the Port Reset bit to a one frome a zero.\r
- //\r
- State &= ~PORSTSC_RESUME;\r
- EhcWriteOpReg (Ehc, Offset, State);\r
- break;\r
+ case EfiUsbPortSuspend:\r
+ //\r
+ // A write of zero to this bit is ignored by the host\r
+ // controller. The host controller will unconditionally\r
+ // set this bit to a zero when:\r
+ // 1. software sets the Forct Port Resume bit to a zero from a one.\r
+ // 2. software sets the Port Reset bit to a one frome a zero.\r
+ //\r
+ State &= ~PORSTSC_RESUME;\r
+ EhcWriteOpReg (Ehc, Offset, State);\r
+ break;\r
\r
- case EfiUsbPortReset:\r
- //\r
- // Clear PORT_RESET means clear the reset signal.\r
- //\r
- State &= ~PORTSC_RESET;\r
- EhcWriteOpReg (Ehc, Offset, State);\r
- break;\r
+ case EfiUsbPortReset:\r
+ //\r
+ // Clear PORT_RESET means clear the reset signal.\r
+ //\r
+ State &= ~PORTSC_RESET;\r
+ EhcWriteOpReg (Ehc, Offset, State);\r
+ break;\r
\r
- case EfiUsbPortOwner:\r
- //\r
- // Clear port owner means this port owned by EHC\r
- //\r
- State &= ~PORTSC_OWNER;\r
- EhcWriteOpReg (Ehc, Offset, State);\r
- break;\r
+ case EfiUsbPortOwner:\r
+ //\r
+ // Clear port owner means this port owned by EHC\r
+ //\r
+ State &= ~PORTSC_OWNER;\r
+ EhcWriteOpReg (Ehc, Offset, State);\r
+ break;\r
\r
- case EfiUsbPortConnectChange:\r
- //\r
- // Clear connect status change\r
- //\r
- State |= PORTSC_CONN_CHANGE;\r
- EhcWriteOpReg (Ehc, Offset, State);\r
- break;\r
+ case EfiUsbPortConnectChange:\r
+ //\r
+ // Clear connect status change\r
+ //\r
+ State |= PORTSC_CONN_CHANGE;\r
+ EhcWriteOpReg (Ehc, Offset, State);\r
+ break;\r
\r
- case EfiUsbPortEnableChange:\r
- //\r
- // Clear enable status change\r
- //\r
- State |= PORTSC_ENABLE_CHANGE;\r
- EhcWriteOpReg (Ehc, Offset, State);\r
- break;\r
+ case EfiUsbPortEnableChange:\r
+ //\r
+ // Clear enable status change\r
+ //\r
+ State |= PORTSC_ENABLE_CHANGE;\r
+ EhcWriteOpReg (Ehc, Offset, State);\r
+ break;\r
\r
- case EfiUsbPortOverCurrentChange:\r
- //\r
- // Clear PortOverCurrent change\r
- //\r
- State |= PORTSC_OVERCUR_CHANGE;\r
- EhcWriteOpReg (Ehc, Offset, State);\r
- break;\r
+ case EfiUsbPortOverCurrentChange:\r
+ //\r
+ // Clear PortOverCurrent change\r
+ //\r
+ State |= PORTSC_OVERCUR_CHANGE;\r
+ EhcWriteOpReg (Ehc, Offset, State);\r
+ break;\r
\r
- case EfiUsbPortPower:\r
- case EfiUsbPortSuspendChange:\r
- case EfiUsbPortResetChange:\r
- //\r
- // Not supported or not related operation\r
- //\r
- break;\r
+ case EfiUsbPortPower:\r
+ case EfiUsbPortSuspendChange:\r
+ case EfiUsbPortResetChange:\r
+ //\r
+ // Not supported or not related operation\r
+ //\r
+ break;\r
\r
- default:\r
- Status = EFI_INVALID_PARAMETER;\r
- break;\r
+ default:\r
+ Status = EFI_INVALID_PARAMETER;\r
+ break;\r
}\r
\r
ON_EXIT:\r
EFI_STATUS\r
EFIAPI\r
EhcSetRootHubPortFeature (\r
- IN EFI_PEI_SERVICES **PeiServices,\r
- IN PEI_USB2_HOST_CONTROLLER_PPI *This,\r
- IN UINT8 PortNumber,\r
- IN EFI_USB_PORT_FEATURE PortFeature\r
+ IN EFI_PEI_SERVICES **PeiServices,\r
+ IN PEI_USB2_HOST_CONTROLLER_PPI *This,\r
+ IN UINT8 PortNumber,\r
+ IN EFI_USB_PORT_FEATURE PortFeature\r
)\r
{\r
- PEI_USB2_HC_DEV *Ehc;\r
- UINT32 Offset;\r
- UINT32 State;\r
- UINT32 TotalPort;\r
- EFI_STATUS Status;\r
+ PEI_USB2_HC_DEV *Ehc;\r
+ UINT32 Offset;\r
+ UINT32 State;\r
+ UINT32 TotalPort;\r
+ EFI_STATUS Status;\r
\r
- Ehc = PEI_RECOVERY_USB_EHC_DEV_FROM_EHCI_THIS (This);\r
- Status = EFI_SUCCESS;\r
+ Ehc = PEI_RECOVERY_USB_EHC_DEV_FROM_EHCI_THIS (This);\r
+ Status = EFI_SUCCESS;\r
\r
TotalPort = (Ehc->HcStructParams & HCSP_NPORTS);\r
\r
goto ON_EXIT;\r
}\r
\r
- Offset = (UINT32) (EHC_PORT_STAT_OFFSET + (4 * PortNumber));\r
- State = EhcReadOpReg (Ehc, Offset);\r
+ Offset = (UINT32)(EHC_PORT_STAT_OFFSET + (4 * PortNumber));\r
+ State = EhcReadOpReg (Ehc, Offset);\r
\r
//\r
// Mask off the port status change bits, these bits are\r
State &= ~PORTSC_CHANGE_MASK;\r
\r
switch (PortFeature) {\r
- case EfiUsbPortEnable:\r
- //\r
- // Sofeware can't set this bit, Port can only be enable by\r
- // EHCI as a part of the reset and enable\r
- //\r
- State |= PORTSC_ENABLED;\r
- EhcWriteOpReg (Ehc, Offset, State);\r
- break;\r
+ case EfiUsbPortEnable:\r
+ //\r
+ // Sofeware can't set this bit, Port can only be enable by\r
+ // EHCI as a part of the reset and enable\r
+ //\r
+ State |= PORTSC_ENABLED;\r
+ EhcWriteOpReg (Ehc, Offset, State);\r
+ break;\r
\r
- case EfiUsbPortSuspend:\r
- State |= PORTSC_SUSPEND;\r
- EhcWriteOpReg (Ehc, Offset, State);\r
- break;\r
+ case EfiUsbPortSuspend:\r
+ State |= PORTSC_SUSPEND;\r
+ EhcWriteOpReg (Ehc, Offset, State);\r
+ break;\r
\r
- case EfiUsbPortReset:\r
- //\r
- // Make sure Host Controller not halt before reset it\r
- //\r
- if (EhcIsHalt (Ehc)) {\r
- Status = EhcRunHC (Ehc, EHC_GENERIC_TIMEOUT);\r
+ case EfiUsbPortReset:\r
+ //\r
+ // Make sure Host Controller not halt before reset it\r
+ //\r
+ if (EhcIsHalt (Ehc)) {\r
+ Status = EhcRunHC (Ehc, EHC_GENERIC_TIMEOUT);\r
\r
- if (EFI_ERROR (Status)) {\r
- break;\r
+ if (EFI_ERROR (Status)) {\r
+ break;\r
+ }\r
}\r
- }\r
\r
- //\r
- // Set one to PortReset bit must also set zero to PortEnable bit\r
- //\r
- State |= PORTSC_RESET;\r
- State &= ~PORTSC_ENABLED;\r
- EhcWriteOpReg (Ehc, Offset, State);\r
- break;\r
+ //\r
+ // Set one to PortReset bit must also set zero to PortEnable bit\r
+ //\r
+ State |= PORTSC_RESET;\r
+ State &= ~PORTSC_ENABLED;\r
+ EhcWriteOpReg (Ehc, Offset, State);\r
+ break;\r
\r
- case EfiUsbPortPower:\r
- //\r
- // Not supported, ignore the operation\r
- //\r
- Status = EFI_SUCCESS;\r
- break;\r
+ case EfiUsbPortPower:\r
+ //\r
+ // Not supported, ignore the operation\r
+ //\r
+ Status = EFI_SUCCESS;\r
+ break;\r
\r
- case EfiUsbPortOwner:\r
- State |= PORTSC_OWNER;\r
- EhcWriteOpReg (Ehc, Offset, State);\r
- break;\r
+ case EfiUsbPortOwner:\r
+ State |= PORTSC_OWNER;\r
+ EhcWriteOpReg (Ehc, Offset, State);\r
+ break;\r
\r
- default:\r
- Status = EFI_INVALID_PARAMETER;\r
+ default:\r
+ Status = EFI_INVALID_PARAMETER;\r
}\r
\r
ON_EXIT:\r
EFI_STATUS\r
EFIAPI\r
EhcGetRootHubPortStatus (\r
- IN EFI_PEI_SERVICES **PeiServices,\r
- IN PEI_USB2_HOST_CONTROLLER_PPI *This,\r
- IN UINT8 PortNumber,\r
- OUT EFI_USB_PORT_STATUS *PortStatus\r
+ IN EFI_PEI_SERVICES **PeiServices,\r
+ IN PEI_USB2_HOST_CONTROLLER_PPI *This,\r
+ IN UINT8 PortNumber,\r
+ OUT EFI_USB_PORT_STATUS *PortStatus\r
)\r
{\r
- PEI_USB2_HC_DEV *Ehc;\r
- UINT32 Offset;\r
- UINT32 State;\r
- UINT32 TotalPort;\r
- UINTN Index;\r
- UINTN MapSize;\r
- EFI_STATUS Status;\r
+ PEI_USB2_HC_DEV *Ehc;\r
+ UINT32 Offset;\r
+ UINT32 State;\r
+ UINT32 TotalPort;\r
+ UINTN Index;\r
+ UINTN MapSize;\r
+ EFI_STATUS Status;\r
\r
if (PortStatus == NULL) {\r
return EFI_INVALID_PARAMETER;\r
}\r
\r
- Ehc = PEI_RECOVERY_USB_EHC_DEV_FROM_EHCI_THIS(This);\r
- Status = EFI_SUCCESS;\r
+ Ehc = PEI_RECOVERY_USB_EHC_DEV_FROM_EHCI_THIS (This);\r
+ Status = EFI_SUCCESS;\r
\r
TotalPort = (Ehc->HcStructParams & HCSP_NPORTS);\r
\r
goto ON_EXIT;\r
}\r
\r
- Offset = (UINT32) (EHC_PORT_STAT_OFFSET + (4 * PortNumber));\r
- PortStatus->PortStatus = 0;\r
- PortStatus->PortChangeStatus = 0;\r
+ Offset = (UINT32)(EHC_PORT_STAT_OFFSET + (4 * PortNumber));\r
+ PortStatus->PortStatus = 0;\r
+ PortStatus->PortChangeStatus = 0;\r
\r
- State = EhcReadOpReg (Ehc, Offset);\r
+ State = EhcReadOpReg (Ehc, Offset);\r
\r
//\r
// Identify device speed. If in K state, it is low speed.\r
//\r
if (EHC_BIT_IS_SET (State, PORTSC_LINESTATE_K)) {\r
PortStatus->PortStatus |= USB_PORT_STAT_LOW_SPEED;\r
-\r
} else if (EHC_BIT_IS_SET (State, PORTSC_ENABLED)) {\r
PortStatus->PortStatus |= USB_PORT_STAT_HIGH_SPEED;\r
}\r
\r
for (Index = 0; Index < MapSize; Index++) {\r
if (EHC_BIT_IS_SET (State, mUsbPortStateMap[Index].HwState)) {\r
- PortStatus->PortStatus = (UINT16) (PortStatus->PortStatus | mUsbPortStateMap[Index].UefiState);\r
+ PortStatus->PortStatus = (UINT16)(PortStatus->PortStatus | mUsbPortStateMap[Index].UefiState);\r
}\r
}\r
\r
\r
for (Index = 0; Index < MapSize; Index++) {\r
if (EHC_BIT_IS_SET (State, mUsbPortChangeMap[Index].HwState)) {\r
- PortStatus->PortChangeStatus = (UINT16) (PortStatus->PortChangeStatus | mUsbPortChangeMap[Index].UefiState);\r
+ PortStatus->PortChangeStatus = (UINT16)(PortStatus->PortChangeStatus | mUsbPortChangeMap[Index].UefiState);\r
}\r
}\r
\r
OUT UINT32 *TransferResult\r
)\r
{\r
- PEI_USB2_HC_DEV *Ehc;\r
- PEI_URB *Urb;\r
- UINT8 Endpoint;\r
- EFI_STATUS Status;\r
+ PEI_USB2_HC_DEV *Ehc;\r
+ PEI_URB *Urb;\r
+ UINT8 Endpoint;\r
+ EFI_STATUS Status;\r
\r
//\r
// Validate parameters\r
\r
if ((TransferDirection != EfiUsbDataIn) &&\r
(TransferDirection != EfiUsbDataOut) &&\r
- (TransferDirection != EfiUsbNoData)) {\r
+ (TransferDirection != EfiUsbNoData))\r
+ {\r
return EFI_INVALID_PARAMETER;\r
}\r
\r
if ((TransferDirection == EfiUsbNoData) &&\r
- ((Data != NULL) || (*DataLength != 0))) {\r
+ ((Data != NULL) || (*DataLength != 0)))\r
+ {\r
return EFI_INVALID_PARAMETER;\r
}\r
\r
if ((TransferDirection != EfiUsbNoData) &&\r
- ((Data == NULL) || (*DataLength == 0))) {\r
+ ((Data == NULL) || (*DataLength == 0)))\r
+ {\r
return EFI_INVALID_PARAMETER;\r
}\r
\r
if ((MaximumPacketLength != 8) && (MaximumPacketLength != 16) &&\r
- (MaximumPacketLength != 32) && (MaximumPacketLength != 64)) {\r
+ (MaximumPacketLength != 32) && (MaximumPacketLength != 64))\r
+ {\r
return EFI_INVALID_PARAMETER;\r
}\r
\r
-\r
if ((DeviceSpeed == EFI_USB_SPEED_LOW) ||\r
((DeviceSpeed == EFI_USB_SPEED_FULL) && (MaximumPacketLength > 64)) ||\r
- ((EFI_USB_SPEED_HIGH == DeviceSpeed) && (MaximumPacketLength > 512))) {\r
+ ((EFI_USB_SPEED_HIGH == DeviceSpeed) && (MaximumPacketLength > 512)))\r
+ {\r
return EFI_INVALID_PARAMETER;\r
}\r
\r
- Ehc = PEI_RECOVERY_USB_EHC_DEV_FROM_EHCI_THIS (This);\r
+ Ehc = PEI_RECOVERY_USB_EHC_DEV_FROM_EHCI_THIS (This);\r
\r
Status = EFI_DEVICE_ERROR;\r
*TransferResult = EFI_USB_ERR_SYSTEM;\r
// endpoint is bidirectional. EhcCreateUrb expects this\r
// combination of Ep addr and its direction.\r
//\r
- Endpoint = (UINT8) (0 | ((TransferDirection == EfiUsbDataIn) ? 0x80 : 0));\r
- Urb = EhcCreateUrb (\r
- Ehc,\r
- DeviceAddress,\r
- Endpoint,\r
- DeviceSpeed,\r
- 0,\r
- MaximumPacketLength,\r
- Translator,\r
- EHC_CTRL_TRANSFER,\r
- Request,\r
- Data,\r
- *DataLength,\r
- NULL,\r
- NULL,\r
- 1\r
- );\r
+ Endpoint = (UINT8)(0 | ((TransferDirection == EfiUsbDataIn) ? 0x80 : 0));\r
+ Urb = EhcCreateUrb (\r
+ Ehc,\r
+ DeviceAddress,\r
+ Endpoint,\r
+ DeviceSpeed,\r
+ 0,\r
+ MaximumPacketLength,\r
+ Translator,\r
+ EHC_CTRL_TRANSFER,\r
+ Request,\r
+ Data,\r
+ *DataLength,\r
+ NULL,\r
+ NULL,\r
+ 1\r
+ );\r
\r
if (Urb == NULL) {\r
Status = EFI_OUT_OF_RESOURCES;\r
IN VOID *Ppi\r
)\r
{\r
- PEI_USB2_HC_DEV *Ehc;\r
+ PEI_USB2_HC_DEV *Ehc;\r
\r
Ehc = PEI_RECOVERY_USB_EHC_DEV_FROM_THIS_NOTIFY (NotifyDescriptor);\r
\r
IN CONST EFI_PEI_SERVICES **PeiServices\r
)\r
{\r
- PEI_USB_CONTROLLER_PPI *ChipSetUsbControllerPpi;\r
- EFI_STATUS Status;\r
- UINT8 Index;\r
- UINTN ControllerType;\r
- UINTN BaseAddress;\r
- UINTN MemPages;\r
- PEI_USB2_HC_DEV *EhcDev;\r
- EFI_PHYSICAL_ADDRESS TempPtr;\r
+ PEI_USB_CONTROLLER_PPI *ChipSetUsbControllerPpi;\r
+ EFI_STATUS Status;\r
+ UINT8 Index;\r
+ UINTN ControllerType;\r
+ UINTN BaseAddress;\r
+ UINTN MemPages;\r
+ PEI_USB2_HC_DEV *EhcDev;\r
+ EFI_PHYSICAL_ADDRESS TempPtr;\r
\r
//\r
// Shadow this PEIM to run from memory\r
&gPeiUsbControllerPpiGuid,\r
0,\r
NULL,\r
- (VOID **) &ChipSetUsbControllerPpi\r
+ (VOID **)&ChipSetUsbControllerPpi\r
);\r
if (EFI_ERROR (Status)) {\r
return EFI_UNSUPPORTED;\r
Index = 0;\r
while (TRUE) {\r
Status = ChipSetUsbControllerPpi->GetUsbController (\r
- (EFI_PEI_SERVICES **) PeiServices,\r
+ (EFI_PEI_SERVICES **)PeiServices,\r
ChipSetUsbControllerPpi,\r
Index,\r
&ControllerType,\r
}\r
\r
MemPages = sizeof (PEI_USB2_HC_DEV) / PAGESIZE + 1;\r
- Status = PeiServicesAllocatePages (\r
- EfiBootServicesCode,\r
- MemPages,\r
- &TempPtr\r
- );\r
+ Status = PeiServicesAllocatePages (\r
+ EfiBootServicesCode,\r
+ MemPages,\r
+ &TempPtr\r
+ );\r
if (EFI_ERROR (Status)) {\r
return EFI_OUT_OF_RESOURCES;\r
}\r
\r
- ZeroMem((VOID *)(UINTN)TempPtr, MemPages*PAGESIZE);\r
- EhcDev = (PEI_USB2_HC_DEV *) ((UINTN) TempPtr);\r
+ ZeroMem ((VOID *)(UINTN)TempPtr, MemPages*PAGESIZE);\r
+ EhcDev = (PEI_USB2_HC_DEV *)((UINTN)TempPtr);\r
\r
EhcDev->Signature = USB2_HC_DEV_SIGNATURE;\r
\r
IoMmuInit (&EhcDev->IoMmu);\r
\r
- EhcDev->UsbHostControllerBaseAddress = (UINT32) BaseAddress;\r
-\r
+ EhcDev->UsbHostControllerBaseAddress = (UINT32)BaseAddress;\r
\r
EhcDev->HcStructParams = EhcReadCapRegister (EhcDev, EHC_HCSPARAMS_OFFSET);\r
EhcDev->HcCapParams = EhcReadCapRegister (EhcDev, EHC_HCCPARAMS_OFFSET);\r
return Status;\r
}\r
\r
- EhcDev->Usb2HostControllerPpi.ControlTransfer = EhcControlTransfer;\r
- EhcDev->Usb2HostControllerPpi.BulkTransfer = EhcBulkTransfer;\r
- EhcDev->Usb2HostControllerPpi.GetRootHubPortNumber = EhcGetRootHubPortNumber;\r
- EhcDev->Usb2HostControllerPpi.GetRootHubPortStatus = EhcGetRootHubPortStatus;\r
- EhcDev->Usb2HostControllerPpi.SetRootHubPortFeature = EhcSetRootHubPortFeature;\r
- EhcDev->Usb2HostControllerPpi.ClearRootHubPortFeature = EhcClearRootHubPortFeature;\r
+ EhcDev->Usb2HostControllerPpi.ControlTransfer = EhcControlTransfer;\r
+ EhcDev->Usb2HostControllerPpi.BulkTransfer = EhcBulkTransfer;\r
+ EhcDev->Usb2HostControllerPpi.GetRootHubPortNumber = EhcGetRootHubPortNumber;\r
+ EhcDev->Usb2HostControllerPpi.GetRootHubPortStatus = EhcGetRootHubPortStatus;\r
+ EhcDev->Usb2HostControllerPpi.SetRootHubPortFeature = EhcSetRootHubPortFeature;\r
+ EhcDev->Usb2HostControllerPpi.ClearRootHubPortFeature = EhcClearRootHubPortFeature;\r
\r
EhcDev->PpiDescriptor.Flags = (EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST);\r
- EhcDev->PpiDescriptor.Guid = &gPeiUsb2HostControllerPpiGuid;\r
- EhcDev->PpiDescriptor.Ppi = &EhcDev->Usb2HostControllerPpi;\r
+ EhcDev->PpiDescriptor.Guid = &gPeiUsb2HostControllerPpiGuid;\r
+ EhcDev->PpiDescriptor.Ppi = &EhcDev->Usb2HostControllerPpi;\r
\r
Status = PeiServicesInstallPpi (&EhcDev->PpiDescriptor);\r
if (EFI_ERROR (Status)) {\r
continue;\r
}\r
\r
- EhcDev->EndOfPeiNotifyList.Flags = (EFI_PEI_PPI_DESCRIPTOR_NOTIFY_CALLBACK | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST);\r
- EhcDev->EndOfPeiNotifyList.Guid = &gEfiEndOfPeiSignalPpiGuid;\r
+ EhcDev->EndOfPeiNotifyList.Flags = (EFI_PEI_PPI_DESCRIPTOR_NOTIFY_CALLBACK | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST);\r
+ EhcDev->EndOfPeiNotifyList.Guid = &gEfiEndOfPeiSignalPpiGuid;\r
EhcDev->EndOfPeiNotifyList.Notify = EhcEndOfPei;\r
\r
PeiServicesNotifyPpi (&EhcDev->EndOfPeiNotifyList);\r
**/\r
EFI_STATUS\r
InitializeUsbHC (\r
- IN PEI_USB2_HC_DEV *EhcDev\r
+ IN PEI_USB2_HC_DEV *EhcDev\r
)\r
{\r
EFI_STATUS Status;\r
\r
-\r
EhcResetHC (EhcDev, EHC_RESET_TIMEOUT);\r
\r
Status = EhcInitHC (EhcDev);\r
projects / mirror_edk2.git / blobdiff