/** @file\r
Private Header file for Usb Host Controller PEIM\r
\r
-Copyright (c) 2010, Intel Corporation. All rights reserved.<BR>\r
- \r
-This program and the accompanying materials\r
-are licensed and made available under the terms and conditions\r
-of the BSD License which accompanies this distribution. The\r
-full text of the license may be found at\r
-http://opensource.org/licenses/bsd-license.php\r
+Copyright (c) 2010 - 2018, Intel Corporation. All rights reserved.<BR>\r
\r
-THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
-WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+SPDX-License-Identifier: BSD-2-Clause-Patent\r
\r
**/\r
\r
#ifndef _EFI_EHCI_REG_H_\r
#define _EFI_EHCI_REG_H_\r
\r
-\r
-\r
//\r
// Capability register offset\r
//\r
-#define EHC_CAPLENGTH_OFFSET 0 // Capability register length offset\r
-#define EHC_HCSPARAMS_OFFSET 0x04 // Structural Parameters 04-07h\r
-#define EHC_HCCPARAMS_OFFSET 0x08 // Capability parameters offset\r
+#define EHC_CAPLENGTH_OFFSET 0 // Capability register length offset\r
+#define EHC_HCSPARAMS_OFFSET 0x04 // Structural Parameters 04-07h\r
+#define EHC_HCCPARAMS_OFFSET 0x08 // Capability parameters offset\r
\r
//\r
// Capability register bit definition\r
//\r
-#define HCSP_NPORTS 0x0F // Number of root hub port\r
-#define HCCP_64BIT 0x01 // 64-bit addressing capability\r
+#define HCSP_NPORTS 0x0F // Number of root hub port\r
+#define HCCP_64BIT 0x01 // 64-bit addressing capability\r
\r
//\r
// Operational register offset\r
#define EHC_CONFIG_FLAG_OFFSET 0x40 // Configure flag register offset\r
#define EHC_PORT_STAT_OFFSET 0x44 // Port status/control offset\r
\r
-#define EHC_FRAME_LEN 1024\r
+#define EHC_FRAME_LEN 1024\r
\r
//\r
// Register bit definition\r
//\r
-#define CONFIGFLAG_ROUTE_EHC 0x01 // Route port to EHC\r
-\r
-#define USBCMD_RUN 0x01 // Run/stop\r
-#define USBCMD_RESET 0x02 // Start the host controller reset\r
-#define USBCMD_ENABLE_PERIOD 0x10 // Enable periodic schedule\r
-#define USBCMD_ENABLE_ASYNC 0x20 // Enable asynchronous schedule\r
-#define USBCMD_IAAD 0x40 // Interrupt on async advance doorbell\r
-\r
-#define USBSTS_IAA 0x20 // Interrupt on async advance\r
-#define USBSTS_PERIOD_ENABLED 0x4000 // Periodic schedule status\r
-#define USBSTS_ASYNC_ENABLED 0x8000 // Asynchronous schedule status\r
-#define USBSTS_HALT 0x1000 // Host controller halted\r
-#define USBSTS_SYS_ERROR 0x10 // Host system error\r
-#define USBSTS_INTACK_MASK 0x003F // Mask for the interrupt ACK, the WC\r
+#define CONFIGFLAG_ROUTE_EHC 0x01 // Route port to EHC\r
+\r
+#define USBCMD_RUN 0x01 // Run/stop\r
+#define USBCMD_RESET 0x02 // Start the host controller reset\r
+#define USBCMD_ENABLE_PERIOD 0x10 // Enable periodic schedule\r
+#define USBCMD_ENABLE_ASYNC 0x20 // Enable asynchronous schedule\r
+#define USBCMD_IAAD 0x40 // Interrupt on async advance doorbell\r
+\r
+#define USBSTS_IAA 0x20 // Interrupt on async advance\r
+#define USBSTS_PERIOD_ENABLED 0x4000 // Periodic schedule status\r
+#define USBSTS_ASYNC_ENABLED 0x8000 // Asynchronous schedule status\r
+#define USBSTS_HALT 0x1000 // Host controller halted\r
+#define USBSTS_SYS_ERROR 0x10 // Host system error\r
+#define USBSTS_INTACK_MASK 0x003F // Mask for the interrupt ACK, the WC\r
// (write clean) bits in USBSTS register\r
\r
-#define PORTSC_CONN 0x01 // Current Connect Status\r
-#define PORTSC_CONN_CHANGE 0x02 // Connect Status Change\r
-#define PORTSC_ENABLED 0x04 // Port Enable / Disable\r
-#define PORTSC_ENABLE_CHANGE 0x08 // Port Enable / Disable Change\r
-#define PORTSC_OVERCUR 0x10 // Over current Active\r
-#define PORTSC_OVERCUR_CHANGE 0x20 // Over current Change\r
-#define PORSTSC_RESUME 0x40 // Force Port Resume\r
-#define PORTSC_SUSPEND 0x80 // Port Suspend State\r
-#define PORTSC_RESET 0x100 // Port Reset\r
-#define PORTSC_LINESTATE_K 0x400 // Line Status K-state\r
-#define PORTSC_LINESTATE_J 0x800 // Line Status J-state\r
-#define PORTSC_POWER 0x1000 // Port Power\r
-#define PORTSC_OWNER 0x2000 // Port Owner\r
-#define PORTSC_CHANGE_MASK 0x2A // Mask of the port change bits,\r
+#define PORTSC_CONN 0x01 // Current Connect Status\r
+#define PORTSC_CONN_CHANGE 0x02 // Connect Status Change\r
+#define PORTSC_ENABLED 0x04 // Port Enable / Disable\r
+#define PORTSC_ENABLE_CHANGE 0x08 // Port Enable / Disable Change\r
+#define PORTSC_OVERCUR 0x10 // Over current Active\r
+#define PORTSC_OVERCUR_CHANGE 0x20 // Over current Change\r
+#define PORSTSC_RESUME 0x40 // Force Port Resume\r
+#define PORTSC_SUSPEND 0x80 // Port Suspend State\r
+#define PORTSC_RESET 0x100 // Port Reset\r
+#define PORTSC_LINESTATE_K 0x400 // Line Status K-state\r
+#define PORTSC_LINESTATE_J 0x800 // Line Status J-state\r
+#define PORTSC_POWER 0x1000 // Port Power\r
+#define PORTSC_OWNER 0x2000 // Port Owner\r
+#define PORTSC_CHANGE_MASK 0x2A // Mask of the port change bits,\r
// they are WC (write clean)\r
//\r
// PCI Configuration Registers\r
//\r
-#define EHC_BAR_INDEX 0 // how many bytes away from USB_BASE to 0x10\r
+#define EHC_BAR_INDEX 0 // how many bytes away from USB_BASE to 0x10\r
\r
-#define EHC_LINK_TERMINATED(Link) (((Link) & 0x01) != 0)\r
+#define EHC_LINK_TERMINATED(Link) (((Link) & 0x01) != 0)\r
\r
#define EHC_ADDR(High, QhHw32) \\r
((VOID *) (UINTN) (LShiftU64 ((High), 32) | ((QhHw32) & 0xFFFFFFF0)))\r
\r
-#define EHCI_IS_DATAIN(EndpointAddr) EHC_BIT_IS_SET((EndpointAddr), 0x80)\r
+#define EHCI_IS_DATAIN(EndpointAddr) EHC_BIT_IS_SET((EndpointAddr), 0x80)\r
\r
//\r
-// Structure to map the hardware port states to the \r
-// UEFI's port states. \r
+// Structure to map the hardware port states to the\r
+// UEFI's port states.\r
//\r
typedef struct {\r
- UINT16 HwState;\r
- UINT16 UefiState;\r
+ UINT16 HwState;\r
+ UINT16 UefiState;\r
} USB_PORT_STATE_MAP;\r
\r
//\r
//\r
#pragma pack(1)\r
typedef struct {\r
- UINT8 Pi;\r
- UINT8 SubClassCode;\r
- UINT8 BaseCode;\r
+ UINT8 Pi;\r
+ UINT8 SubClassCode;\r
+ UINT8 BaseCode;\r
} USB_CLASSC;\r
#pragma pack()\r
\r
-\r
/**\r
Read EHCI capability register.\r
- \r
+\r
@param Ehc The EHCI device.\r
@param Offset Capability register address.\r
\r
**/\r
UINT32\r
EhcReadCapRegister (\r
- IN PEI_USB2_HC_DEV *Ehc,\r
- IN UINT32 Offset\r
+ IN PEI_USB2_HC_DEV *Ehc,\r
+ IN UINT32 Offset\r
)\r
;\r
\r
/**\r
Read Ehc Operation register.\r
- \r
+\r
@param Ehc The EHCI device.\r
@param Offset The operation register offset.\r
\r
**/\r
UINT32\r
EhcReadOpReg (\r
- IN PEI_USB2_HC_DEV *Ehc,\r
- IN UINT32 Offset\r
+ IN PEI_USB2_HC_DEV *Ehc,\r
+ IN UINT32 Offset\r
)\r
;\r
\r
/**\r
Write the data to the EHCI operation register.\r
- \r
+\r
@param Ehc The EHCI device.\r
@param Offset EHCI operation register offset.\r
@param Data The data to write.\r
**/\r
VOID\r
EhcWriteOpReg (\r
- IN PEI_USB2_HC_DEV *Ehc,\r
- IN UINT32 Offset,\r
- IN UINT32 Data\r
+ IN PEI_USB2_HC_DEV *Ehc,\r
+ IN UINT32 Offset,\r
+ IN UINT32 Data\r
)\r
;\r
\r
/**\r
Stop the legacy USB SMI support.\r
- \r
+\r
@param Ehc The EHCI device.\r
\r
**/\r
VOID\r
EhcClearLegacySupport (\r
- IN PEI_USB2_HC_DEV *Ehc\r
+ IN PEI_USB2_HC_DEV *Ehc\r
)\r
;\r
\r
/**\r
Set door bell and wait it to be ACKed by host controller.\r
This function is used to synchronize with the hardware.\r
- \r
+\r
@param Ehc The EHCI device.\r
@param Timeout The time to wait before abort (in millisecond, ms).\r
\r
**/\r
EFI_STATUS\r
EhcSetAndWaitDoorBell (\r
- IN PEI_USB2_HC_DEV *Ehc,\r
- IN UINT32 Timeout\r
+ IN PEI_USB2_HC_DEV *Ehc,\r
+ IN UINT32 Timeout\r
)\r
;\r
\r
/**\r
- Clear all the interrutp status bits, these bits \r
+ Clear all the interrutp status bits, these bits\r
are Write-Clean.\r
- \r
+\r
@param Ehc The EHCI device.\r
\r
**/\r
VOID\r
EhcAckAllInterrupt (\r
- IN PEI_USB2_HC_DEV *Ehc\r
+ IN PEI_USB2_HC_DEV *Ehc\r
)\r
;\r
\r
/**\r
Check whether Ehc is halted.\r
- \r
+\r
@param Ehc The EHCI device.\r
\r
@retval TRUE The controller is halted.\r
**/\r
BOOLEAN\r
EhcIsHalt (\r
- IN PEI_USB2_HC_DEV *Ehc\r
+ IN PEI_USB2_HC_DEV *Ehc\r
)\r
;\r
\r
/**\r
Check whether system error occurred.\r
- \r
+\r
@param Ehc The EHCI device.\r
\r
@retval TRUE System error happened.\r
**/\r
BOOLEAN\r
EhcIsSysError (\r
- IN PEI_USB2_HC_DEV *Ehc\r
+ IN PEI_USB2_HC_DEV *Ehc\r
)\r
;\r
\r
/**\r
Reset the host controller.\r
- \r
+\r
@param Ehc The EHCI device.\r
@param Timeout Time to wait before abort (in millisecond, ms).\r
\r
**/\r
EFI_STATUS\r
EhcResetHC (\r
- IN PEI_USB2_HC_DEV *Ehc,\r
- IN UINT32 Timeout\r
+ IN PEI_USB2_HC_DEV *Ehc,\r
+ IN UINT32 Timeout\r
)\r
;\r
\r
/**\r
Halt the host controller.\r
- \r
+\r
@param Ehc The EHCI device.\r
@param Timeout Time to wait before abort.\r
\r
**/\r
EFI_STATUS\r
EhcHaltHC (\r
- IN PEI_USB2_HC_DEV *Ehc,\r
- IN UINT32 Timeout\r
+ IN PEI_USB2_HC_DEV *Ehc,\r
+ IN UINT32 Timeout\r
)\r
;\r
\r
/**\r
Set the EHCI to run\r
- \r
+\r
@param Ehc The EHCI device.\r
@param Timeout Time to wait before abort.\r
\r
**/\r
EFI_STATUS\r
EhcRunHC (\r
- IN PEI_USB2_HC_DEV *Ehc,\r
- IN UINT32 Timeout\r
+ IN PEI_USB2_HC_DEV *Ehc,\r
+ IN UINT32 Timeout\r
)\r
;\r
\r
/**\r
- Initialize the HC hardware. \r
+ Initialize the HC hardware.\r
EHCI spec lists the five things to do to initialize the hardware.\r
1. Program CTRLDSSEGMENT.\r
2. Set USBINTR to enable interrupts.\r
3. Set periodic list base.\r
4. Set USBCMD, interrupt threshold, frame list size etc.\r
5. Write 1 to CONFIGFLAG to route all ports to EHCI.\r
- \r
+\r
@param Ehc The EHCI device.\r
\r
@retval EFI_SUCCESS The EHCI has come out of halt state.\r
**/\r
EFI_STATUS\r
EhcInitHC (\r
- IN PEI_USB2_HC_DEV *Ehc\r
+ IN PEI_USB2_HC_DEV *Ehc\r
)\r
;\r
\r
projects / mirror_edk2.git / blobdiff