MdeModulePkg: Change use of EFI_D_* to DEBUG_*

[mirror_edk2.git] / MdeModulePkg / Bus / Pci / NvmExpressDxe / NvmExpressHci.c

diff --git a/MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpressHci.c b/MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpressHci.c
index 450d372b2faacb524be03477bd90a7eb08d5cd5f..08f9d50ff5de60788df6761392b34959ed7de7a3 100644 (file)
--- a/MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpressHci.c
+++ b/MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpressHci.c
@@ -128,13 +128,13 @@ WriteNvmeControllerConfiguration (
     return Status;\r
   }\r
 \r
-  DEBUG ((EFI_D_INFO, "Cc.En: %d\n", Cc->En));\r
-  DEBUG ((EFI_D_INFO, "Cc.Css: %d\n", Cc->Css));\r
-  DEBUG ((EFI_D_INFO, "Cc.Mps: %d\n", Cc->Mps));\r
-  DEBUG ((EFI_D_INFO, "Cc.Ams: %d\n", Cc->Ams));\r
-  DEBUG ((EFI_D_INFO, "Cc.Shn: %d\n", Cc->Shn));\r
-  DEBUG ((EFI_D_INFO, "Cc.Iosqes: %d\n", Cc->Iosqes));\r
-  DEBUG ((EFI_D_INFO, "Cc.Iocqes: %d\n", Cc->Iocqes));\r
+  DEBUG ((DEBUG_INFO, "Cc.En: %d\n", Cc->En));\r
+  DEBUG ((DEBUG_INFO, "Cc.Css: %d\n", Cc->Css));\r
+  DEBUG ((DEBUG_INFO, "Cc.Mps: %d\n", Cc->Mps));\r
+  DEBUG ((DEBUG_INFO, "Cc.Ams: %d\n", Cc->Ams));\r
+  DEBUG ((DEBUG_INFO, "Cc.Shn: %d\n", Cc->Shn));\r
+  DEBUG ((DEBUG_INFO, "Cc.Iosqes: %d\n", Cc->Iosqes));\r
+  DEBUG ((DEBUG_INFO, "Cc.Iocqes: %d\n", Cc->Iocqes));\r
 \r
   return EFI_SUCCESS;\r
 }\r
@@ -214,8 +214,8 @@ WriteNvmeAdminQueueAttributes (
     return Status;\r
   }\r
 \r
-  DEBUG ((EFI_D_INFO, "Aqa.Asqs: %d\n", Aqa->Asqs));\r
-  DEBUG ((EFI_D_INFO, "Aqa.Acqs: %d\n", Aqa->Acqs));\r
+  DEBUG ((DEBUG_INFO, "Aqa.Asqs: %d\n", Aqa->Asqs));\r
+  DEBUG ((DEBUG_INFO, "Aqa.Acqs: %d\n", Aqa->Acqs));\r
 \r
   return EFI_SUCCESS;\r
 }\r
@@ -257,7 +257,7 @@ WriteNvmeAdminSubmissionQueueBaseAddress (
     return Status;\r
   }\r
 \r
-  DEBUG ((EFI_D_INFO, "Asq: %lx\n", *Asq));\r
+  DEBUG ((DEBUG_INFO, "Asq: %lx\n", *Asq));\r
 \r
   return EFI_SUCCESS;\r
 }\r
@@ -300,7 +300,7 @@ WriteNvmeAdminCompletionQueueBaseAddress (
     return Status;\r
   }\r
 \r
-  DEBUG ((EFI_D_INFO, "Acq: %lxh\n", *Acq));\r
+  DEBUG ((DEBUG_INFO, "Acq: %lxh\n", *Acq));\r
 \r
   return EFI_SUCCESS;\r
 }\r
@@ -379,7 +379,7 @@ NvmeDisableController (
       );\r
   }\r
 \r
-  DEBUG ((EFI_D_INFO, "NVMe controller is disabled with status [%r].\n", Status));\r
+  DEBUG ((DEBUG_INFO, "NVMe controller is disabled with status [%r].\n", Status));\r
   return Status;\r
 }\r
 \r
@@ -453,7 +453,7 @@ NvmeEnableController (
       );\r
   }\r
 \r
-  DEBUG ((EFI_D_INFO, "NVMe controller is enabled with status [%r].\n", Status));\r
+  DEBUG ((DEBUG_INFO, "NVMe controller is enabled with status [%r].\n", Status));\r
   return Status;\r
 }\r
 \r
@@ -764,7 +764,7 @@ NvmeControllerInit (
   }\r
 \r
   if (EFI_ERROR (Status)) {\r
-    DEBUG ((EFI_D_INFO, "NvmeControllerInit: failed to enable controller\n"));\r
+    DEBUG ((DEBUG_INFO, "NvmeControllerInit: failed to enable controller\n"));\r
     return Status;\r
   }\r
 \r
@@ -778,7 +778,7 @@ NvmeControllerInit (
                     NULL\r
                     );\r
   if (EFI_ERROR (Status)) {\r
-    DEBUG ((EFI_D_WARN, "NvmeControllerInit: failed to enable 64-bit DMA (%r)\n", Status));\r
+    DEBUG ((DEBUG_WARN, "NvmeControllerInit: failed to enable 64-bit DMA (%r)\n", Status));\r
   }\r
 \r
   //\r
@@ -790,7 +790,7 @@ NvmeControllerInit (
   }\r
 \r
   if (Private->Cap.Css != 0x01) {\r
-    DEBUG ((EFI_D_INFO, "NvmeControllerInit: the controller doesn't support NVMe command set\n"));\r
+    DEBUG ((DEBUG_INFO, "NvmeControllerInit: the controller doesn't support NVMe command set\n"));\r
     return EFI_UNSUPPORTED;\r
   }\r
 \r
@@ -854,15 +854,15 @@ NvmeControllerInit (
   Private->CqBuffer[2]        = (NVME_CQ *)(UINTN)(Private->Buffer + 5 * EFI_PAGE_SIZE);\r
   Private->CqBufferPciAddr[2] = (NVME_CQ *)(UINTN)(Private->BufferPciAddr + 5 * EFI_PAGE_SIZE);\r
 \r
-  DEBUG ((EFI_D_INFO, "Private->Buffer = [%016X]\n", (UINT64)(UINTN)Private->Buffer));\r
-  DEBUG ((EFI_D_INFO, "Admin     Submission Queue size (Aqa.Asqs) = [%08X]\n", Aqa.Asqs));\r
-  DEBUG ((EFI_D_INFO, "Admin     Completion Queue size (Aqa.Acqs) = [%08X]\n", Aqa.Acqs));\r
-  DEBUG ((EFI_D_INFO, "Admin     Submission Queue (SqBuffer[0]) = [%016X]\n", Private->SqBuffer[0]));\r
-  DEBUG ((EFI_D_INFO, "Admin     Completion Queue (CqBuffer[0]) = [%016X]\n", Private->CqBuffer[0]));\r
-  DEBUG ((EFI_D_INFO, "Sync  I/O Submission Queue (SqBuffer[1]) = [%016X]\n", Private->SqBuffer[1]));\r
-  DEBUG ((EFI_D_INFO, "Sync  I/O Completion Queue (CqBuffer[1]) = [%016X]\n", Private->CqBuffer[1]));\r
-  DEBUG ((EFI_D_INFO, "Async I/O Submission Queue (SqBuffer[2]) = [%016X]\n", Private->SqBuffer[2]));\r
-  DEBUG ((EFI_D_INFO, "Async I/O Completion Queue (CqBuffer[2]) = [%016X]\n", Private->CqBuffer[2]));\r
+  DEBUG ((DEBUG_INFO, "Private->Buffer = [%016X]\n", (UINT64)(UINTN)Private->Buffer));\r
+  DEBUG ((DEBUG_INFO, "Admin     Submission Queue size (Aqa.Asqs) = [%08X]\n", Aqa.Asqs));\r
+  DEBUG ((DEBUG_INFO, "Admin     Completion Queue size (Aqa.Acqs) = [%08X]\n", Aqa.Acqs));\r
+  DEBUG ((DEBUG_INFO, "Admin     Submission Queue (SqBuffer[0]) = [%016X]\n", Private->SqBuffer[0]));\r
+  DEBUG ((DEBUG_INFO, "Admin     Completion Queue (CqBuffer[0]) = [%016X]\n", Private->CqBuffer[0]));\r
+  DEBUG ((DEBUG_INFO, "Sync  I/O Submission Queue (SqBuffer[1]) = [%016X]\n", Private->SqBuffer[1]));\r
+  DEBUG ((DEBUG_INFO, "Sync  I/O Completion Queue (CqBuffer[1]) = [%016X]\n", Private->CqBuffer[1]));\r
+  DEBUG ((DEBUG_INFO, "Async I/O Submission Queue (SqBuffer[2]) = [%016X]\n", Private->SqBuffer[2]));\r
+  DEBUG ((DEBUG_INFO, "Async I/O Completion Queue (CqBuffer[2]) = [%016X]\n", Private->CqBuffer[2]));\r
 \r
   //\r
   // Program admin queue attributes.\r
@@ -925,20 +925,20 @@ NvmeControllerInit (
   Sn[20] = 0;\r
   CopyMem (Mn, Private->ControllerData->Mn, sizeof (Private->ControllerData->Mn));\r
   Mn[40] = 0;\r
-  DEBUG ((EFI_D_INFO, " == NVME IDENTIFY CONTROLLER DATA ==\n"));\r
-  DEBUG ((EFI_D_INFO, "    PCI VID   : 0x%x\n", Private->ControllerData->Vid));\r
-  DEBUG ((EFI_D_INFO, "    PCI SSVID : 0x%x\n", Private->ControllerData->Ssvid));\r
-  DEBUG ((EFI_D_INFO, "    SN        : %a\n",   Sn));\r
-  DEBUG ((EFI_D_INFO, "    MN        : %a\n",   Mn));\r
-  DEBUG ((EFI_D_INFO, "    FR        : 0x%x\n", *((UINT64*)Private->ControllerData->Fr)));\r
+  DEBUG ((DEBUG_INFO, " == NVME IDENTIFY CONTROLLER DATA ==\n"));\r
+  DEBUG ((DEBUG_INFO, "    PCI VID   : 0x%x\n", Private->ControllerData->Vid));\r
+  DEBUG ((DEBUG_INFO, "    PCI SSVID : 0x%x\n", Private->ControllerData->Ssvid));\r
+  DEBUG ((DEBUG_INFO, "    SN        : %a\n",   Sn));\r
+  DEBUG ((DEBUG_INFO, "    MN        : %a\n",   Mn));\r
+  DEBUG ((DEBUG_INFO, "    FR        : 0x%x\n", *((UINT64*)Private->ControllerData->Fr)));\r
   DEBUG ((DEBUG_INFO, "    TNVMCAP (high 8-byte) : 0x%lx\n", *((UINT64*)(Private->ControllerData->Tnvmcap + 8))));\r
   DEBUG ((DEBUG_INFO, "    TNVMCAP (low 8-byte)  : 0x%lx\n", *((UINT64*)Private->ControllerData->Tnvmcap)));\r
-  DEBUG ((EFI_D_INFO, "    RAB       : 0x%x\n", Private->ControllerData->Rab));\r
-  DEBUG ((EFI_D_INFO, "    IEEE      : 0x%x\n", *(UINT32*)Private->ControllerData->Ieee_oui));\r
-  DEBUG ((EFI_D_INFO, "    AERL      : 0x%x\n", Private->ControllerData->Aerl));\r
-  DEBUG ((EFI_D_INFO, "    SQES      : 0x%x\n", Private->ControllerData->Sqes));\r
-  DEBUG ((EFI_D_INFO, "    CQES      : 0x%x\n", Private->ControllerData->Cqes));\r
-  DEBUG ((EFI_D_INFO, "    NN        : 0x%x\n", Private->ControllerData->Nn));\r
+  DEBUG ((DEBUG_INFO, "    RAB       : 0x%x\n", Private->ControllerData->Rab));\r
+  DEBUG ((DEBUG_INFO, "    IEEE      : 0x%x\n", *(UINT32*)Private->ControllerData->Ieee_oui));\r
+  DEBUG ((DEBUG_INFO, "    AERL      : 0x%x\n", Private->ControllerData->Aerl));\r
+  DEBUG ((DEBUG_INFO, "    SQES      : 0x%x\n", Private->ControllerData->Sqes));\r
+  DEBUG ((DEBUG_INFO, "    CQES      : 0x%x\n", Private->ControllerData->Cqes));\r
+  DEBUG ((DEBUG_INFO, "    NN        : 0x%x\n", Private->ControllerData->Nn));\r
 \r
   //\r
   // Create two I/O completion queues.\r