MdeModulePkg: Convert all .uni files to utf-8

[mirror_edk2.git] / MdeModulePkg / Bus / Pci / NvmExpressDxe / NvmExpressHci.h

diff --git a/MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpressHci.h b/MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpressHci.h
index aa0ac35c308548fb833111179245fa0346d87a5e..06c1db7d8e915e996400a559ae2ce65215af0a29 100644 (file)
--- a/MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpressHci.h
+++ b/MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpressHci.h
@@ -2,7 +2,7 @@
   NvmExpressDxe driver is used to manage non-volatile memory subsystem which follows\r
   NVM Express specification.\r
 \r
-  Copyright (c) 2013 - 2014, Intel Corporation. All rights reserved.<BR>\r
+  Copyright (c) 2013 - 2015, Intel Corporation. All rights reserved.<BR>\r
   This program and the accompanying materials\r
   are licensed and made available under the terms and conditions of the BSD License\r
   which accompanies this distribution.  The full text of the license may be found at\r
@@ -348,6 +348,10 @@ typedef struct {
   // Admin Command Set Attributes\r
   //\r
   UINT16 Oacs;                /* Optional Admin Command Support */\r
+    #define NAMESPACE_MANAGEMENT_SUPPORTED  BIT3\r
+    #define FW_DOWNLOAD_ACTIVATE_SUPPORTED  BIT2\r
+    #define FORMAT_NVM_SUPPORTED            BIT1\r
+    #define SECURITY_SEND_RECEIVE_SUPPORTED BIT0\r
   UINT8  Acl;                 /* Abort Command Limit */\r
   UINT8  Aerl;                /* Async Event Request Limit */\r
   UINT8  Frmw;                /* Firmware updates */\r
@@ -556,9 +560,9 @@ typedef struct {
   // CDW 10\r
   //\r
   UINT32 Lid:8;               /* Log Page Identifier */\r
-    #define LID_ERROR_INFO\r
-    #define LID_SMART_INFO\r
-    #define LID_FW_SLOT_INFO\r
+    #define LID_ERROR_INFO   0x1\r
+    #define LID_SMART_INFO   0x2\r
+    #define LID_FW_SLOT_INFO 0x3\r
   UINT32 Rsvd1:8;\r
   UINT32 Numd:12;             /* Number of Dwords */\r
   UINT32 Rsvd2:4;             /* Reserved as of Nvm Express 1.1 Spec */\r
@@ -724,9 +728,23 @@ typedef struct {
 //\r
 // Nvm Express Admin cmd opcodes\r
 //\r
-#define NVME_ADMIN_CRIOSQ_OPC                1\r
-#define NVME_ADMIN_CRIOCQ_OPC                5\r
-#define NVME_ADMIN_IDENTIFY_OPC              6\r
+#define NVME_ADMIN_DEIOSQ_CMD                0x00\r
+#define NVME_ADMIN_CRIOSQ_CMD                0x01\r
+#define NVME_ADMIN_GET_LOG_PAGE_CMD          0x02\r
+#define NVME_ADMIN_DEIOCQ_CMD                0x04\r
+#define NVME_ADMIN_CRIOCQ_CMD                0x05\r
+#define NVME_ADMIN_IDENTIFY_CMD              0x06\r
+#define NVME_ADMIN_ABORT_CMD                 0x08\r
+#define NVME_ADMIN_SET_FEATURES_CMD          0x09\r
+#define NVME_ADMIN_GET_FEATURES_CMD          0x0A\r
+#define NVME_ADMIN_ASYNC_EVENT_REQUEST_CMD   0x0C\r
+#define NVME_ADMIN_NAMESACE_MANAGEMENT_CMD   0x0D\r
+#define NVME_ADMIN_FW_COMMIT_CMD             0x10\r
+#define NVME_ADMIN_FW_IAMGE_DOWNLOAD_CMD     0x11\r
+#define NVME_ADMIN_NAMESACE_ATTACHMENT_CMD   0x15\r
+#define NVME_ADMIN_FORMAT_NVM_CMD            0x80\r
+#define NVME_ADMIN_SECURITY_SEND_CMD         0x81\r
+#define NVME_ADMIN_SECURITY_RECEIVE_CMD      0x82\r
 \r
 #define NVME_IO_FLUSH_OPC                    0\r
 #define NVME_IO_WRITE_OPC                    1\r