NVM Express specification.\r
\r
(C) Copyright 2014 Hewlett-Packard Development Company, L.P.<BR>\r
- Copyright (c) 2013 - 2017, Intel Corporation. All rights reserved.<BR>\r
+ Copyright (c) 2013 - 2018, Intel Corporation. All rights reserved.<BR>\r
This program and the accompanying materials\r
are licensed and made available under the terms and conditions of the BSD License\r
which accompanies this distribution. The full text of the license may be found at\r
// these two cmds are special which requires their data buffer must support simultaneous access by both the\r
// processor and a PCI Bus Master. It's caller's responsbility to ensure this.\r
//\r
- if (((Sq->Opc & (BIT0 | BIT1)) != 0) && (Sq->Opc != NVME_ADMIN_CRIOCQ_CMD) && (Sq->Opc != NVME_ADMIN_CRIOSQ_CMD)) {\r
+ if (((Sq->Opc & (BIT0 | BIT1)) != 0) &&\r
+ !((Packet->QueueType == NVME_ADMIN_QUEUE) && ((Sq->Opc == NVME_ADMIN_CRIOCQ_CMD) || (Sq->Opc == NVME_ADMIN_CRIOSQ_CMD)))) {\r
if ((Packet->TransferLength == 0) || (Packet->TransferBuffer == NULL)) {\r
return EFI_INVALID_PARAMETER;\r
}\r