**/\r
EFI_STATUS\r
NvmeMmioRead (\r
- IN OUT VOID *MemBuffer,\r
- IN UINTN MmioAddr,\r
- IN UINTN Size\r
+ IN OUT VOID *MemBuffer,\r
+ IN UINTN MmioAddr,\r
+ IN UINTN Size\r
)\r
{\r
- UINTN Offset;\r
- UINT8 Data;\r
- UINT8 *Ptr;\r
+ UINTN Offset;\r
+ UINT8 Data;\r
+ UINT8 *Ptr;\r
\r
// priority has adjusted\r
switch (Size) {\r
default:\r
Ptr = (UINT8 *)MemBuffer;\r
for (Offset = 0; Offset < Size; Offset += 1) {\r
- Data = MmioRead8 (MmioAddr + Offset);\r
+ Data = MmioRead8 (MmioAddr + Offset);\r
Ptr[Offset] = Data;\r
}\r
+\r
break;\r
}\r
\r
**/\r
EFI_STATUS\r
NvmeMmioWrite (\r
- IN OUT UINTN MmioAddr,\r
- IN VOID *MemBuffer,\r
- IN UINTN Size\r
+ IN OUT UINTN MmioAddr,\r
+ IN VOID *MemBuffer,\r
+ IN UINTN Size\r
)\r
{\r
- UINTN Offset;\r
- UINT8 Data;\r
- UINT8 *Ptr;\r
+ UINTN Offset;\r
+ UINT8 Data;\r
+ UINT8 *Ptr;\r
\r
// priority has adjusted\r
switch (Size) {\r
Data = Ptr[Offset];\r
MmioWrite8 (MmioAddr + Offset, Data);\r
}\r
+\r
break;\r
}\r
\r
**/\r
UINT32\r
NvmeBaseMemPageOffset (\r
- IN UINTN BaseMemIndex\r
+ IN UINTN BaseMemIndex\r
)\r
{\r
- UINT32 Pages;\r
- UINTN Index;\r
- UINT32 PageSizeList[5];\r
+ UINT32 Pages;\r
+ UINTN Index;\r
+ UINT32 PageSizeList[5];\r
\r
- PageSizeList[0] = 1; /* ASQ */\r
- PageSizeList[1] = 1; /* ACQ */\r
- PageSizeList[2] = 1; /* SQs */\r
- PageSizeList[3] = 1; /* CQs */\r
- PageSizeList[4] = NVME_PRP_SIZE; /* PRPs */\r
+ PageSizeList[0] = 1; /* ASQ */\r
+ PageSizeList[1] = 1; /* ACQ */\r
+ PageSizeList[2] = 1; /* SQs */\r
+ PageSizeList[3] = 1; /* CQs */\r
+ PageSizeList[4] = NVME_PRP_SIZE; /* PRPs */\r
\r
if (BaseMemIndex > MAX_BASEMEM_COUNT) {\r
DEBUG ((DEBUG_ERROR, "%a: The input BaseMem index is invalid.\n", __FUNCTION__));\r
**/\r
EFI_STATUS\r
NvmeWaitController (\r
- IN PEI_NVME_CONTROLLER_PRIVATE_DATA *Private,\r
- IN BOOLEAN WaitReady\r
+ IN PEI_NVME_CONTROLLER_PRIVATE_DATA *Private,\r
+ IN BOOLEAN WaitReady\r
)\r
{\r
- NVME_CSTS Csts;\r
- EFI_STATUS Status;\r
- UINT32 Index;\r
- UINT8 Timeout;\r
+ NVME_CSTS Csts;\r
+ EFI_STATUS Status;\r
+ UINT32 Index;\r
+ UINT8 Timeout;\r
\r
//\r
// Cap.To specifies max delay time in 500ms increments for Csts.Rdy to set after\r
}\r
\r
Status = EFI_SUCCESS;\r
- for(Index = (Timeout * 500); Index != 0; --Index) {\r
+ for (Index = (Timeout * 500); Index != 0; --Index) {\r
MicroSecondDelay (1000);\r
\r
//\r
// Check if the controller is initialized\r
//\r
Status = NVME_GET_CSTS (Private, &Csts);\r
- if (EFI_ERROR(Status)) {\r
+ if (EFI_ERROR (Status)) {\r
DEBUG ((DEBUG_ERROR, "%a: NVME_GET_CSTS fail, Status - %r\n", __FUNCTION__, Status));\r
return Status;\r
}\r
\r
- if ((BOOLEAN) Csts.Rdy == WaitReady) {\r
+ if ((BOOLEAN)Csts.Rdy == WaitReady) {\r
break;\r
}\r
}\r
**/\r
EFI_STATUS\r
NvmeDisableController (\r
- IN PEI_NVME_CONTROLLER_PRIVATE_DATA *Private\r
+ IN PEI_NVME_CONTROLLER_PRIVATE_DATA *Private\r
)\r
{\r
- NVME_CC Cc;\r
- NVME_CSTS Csts;\r
- EFI_STATUS Status;\r
+ NVME_CC Cc;\r
+ NVME_CSTS Csts;\r
+ EFI_STATUS Status;\r
\r
Status = NVME_GET_CSTS (Private, &Csts);\r
\r
**/\r
EFI_STATUS\r
NvmeEnableController (\r
- IN PEI_NVME_CONTROLLER_PRIVATE_DATA *Private\r
+ IN PEI_NVME_CONTROLLER_PRIVATE_DATA *Private\r
)\r
{\r
- NVME_CC Cc;\r
- EFI_STATUS Status;\r
+ NVME_CC Cc;\r
+ EFI_STATUS Status;\r
\r
//\r
// Enable the controller\r
**/\r
EFI_STATUS\r
NvmeIdentifyController (\r
- IN PEI_NVME_CONTROLLER_PRIVATE_DATA *Private,\r
- IN VOID *Buffer\r
+ IN PEI_NVME_CONTROLLER_PRIVATE_DATA *Private,\r
+ IN VOID *Buffer\r
)\r
{\r
- EFI_NVM_EXPRESS_PASS_THRU_COMMAND_PACKET CommandPacket;\r
- EFI_NVM_EXPRESS_COMMAND Command;\r
- EFI_NVM_EXPRESS_COMPLETION Completion;\r
- EFI_STATUS Status;\r
+ EFI_NVM_EXPRESS_PASS_THRU_COMMAND_PACKET CommandPacket;\r
+ EFI_NVM_EXPRESS_COMMAND Command;\r
+ EFI_NVM_EXPRESS_COMPLETION Completion;\r
+ EFI_STATUS Status;\r
\r
- ZeroMem (&CommandPacket, sizeof(EFI_NVM_EXPRESS_PASS_THRU_COMMAND_PACKET));\r
- ZeroMem (&Command, sizeof(EFI_NVM_EXPRESS_COMMAND));\r
- ZeroMem (&Completion, sizeof(EFI_NVM_EXPRESS_COMPLETION));\r
+ ZeroMem (&CommandPacket, sizeof (EFI_NVM_EXPRESS_PASS_THRU_COMMAND_PACKET));\r
+ ZeroMem (&Command, sizeof (EFI_NVM_EXPRESS_COMMAND));\r
+ ZeroMem (&Completion, sizeof (EFI_NVM_EXPRESS_COMPLETION));\r
\r
Command.Cdw0.Opcode = NVME_ADMIN_IDENTIFY_CMD;\r
//\r
// According to Nvm Express 1.1 spec Figure 38, When not used, the field shall be cleared to 0h.\r
// For the Identify command, the Namespace Identifier is only used for the Namespace Data structure.\r
//\r
- Command.Nsid = 0;\r
+ Command.Nsid = 0;\r
\r
CommandPacket.NvmeCmd = &Command;\r
CommandPacket.NvmeCompletion = &Completion;\r
**/\r
EFI_STATUS\r
NvmeIdentifyNamespace (\r
- IN PEI_NVME_CONTROLLER_PRIVATE_DATA *Private,\r
- IN UINT32 NamespaceId,\r
- IN VOID *Buffer\r
+ IN PEI_NVME_CONTROLLER_PRIVATE_DATA *Private,\r
+ IN UINT32 NamespaceId,\r
+ IN VOID *Buffer\r
)\r
{\r
- EFI_NVM_EXPRESS_PASS_THRU_COMMAND_PACKET CommandPacket;\r
- EFI_NVM_EXPRESS_COMMAND Command;\r
- EFI_NVM_EXPRESS_COMPLETION Completion;\r
- EFI_STATUS Status;\r
+ EFI_NVM_EXPRESS_PASS_THRU_COMMAND_PACKET CommandPacket;\r
+ EFI_NVM_EXPRESS_COMMAND Command;\r
+ EFI_NVM_EXPRESS_COMPLETION Completion;\r
+ EFI_STATUS Status;\r
\r
- ZeroMem (&CommandPacket, sizeof(EFI_NVM_EXPRESS_PASS_THRU_COMMAND_PACKET));\r
- ZeroMem (&Command, sizeof(EFI_NVM_EXPRESS_COMMAND));\r
- ZeroMem (&Completion, sizeof(EFI_NVM_EXPRESS_COMPLETION));\r
+ ZeroMem (&CommandPacket, sizeof (EFI_NVM_EXPRESS_PASS_THRU_COMMAND_PACKET));\r
+ ZeroMem (&Command, sizeof (EFI_NVM_EXPRESS_COMMAND));\r
+ ZeroMem (&Completion, sizeof (EFI_NVM_EXPRESS_COMPLETION));\r
\r
Command.Cdw0.Opcode = NVME_ADMIN_IDENTIFY_CMD;\r
Command.Nsid = NamespaceId;\r
**/\r
VOID\r
NvmeDumpControllerData (\r
- IN NVME_ADMIN_CONTROLLER_DATA *ControllerData\r
+ IN NVME_ADMIN_CONTROLLER_DATA *ControllerData\r
)\r
{\r
- UINT8 Sn[21];\r
- UINT8 Mn[41];\r
+ UINT8 Sn[21];\r
+ UINT8 Mn[41];\r
\r
CopyMem (Sn, ControllerData->Sn, sizeof (ControllerData->Sn));\r
Sn[20] = 0;\r
DEBUG ((DEBUG_INFO, " == NVME IDENTIFY CONTROLLER DATA ==\n"));\r
DEBUG ((DEBUG_INFO, " PCI VID : 0x%x\n", ControllerData->Vid));\r
DEBUG ((DEBUG_INFO, " PCI SSVID : 0x%x\n", ControllerData->Ssvid));\r
- DEBUG ((DEBUG_INFO, " SN : %a\n", Sn));\r
- DEBUG ((DEBUG_INFO, " MN : %a\n", Mn));\r
- DEBUG ((DEBUG_INFO, " FR : 0x%lx\n", *((UINT64*)ControllerData->Fr)));\r
+ DEBUG ((DEBUG_INFO, " SN : %a\n", Sn));\r
+ DEBUG ((DEBUG_INFO, " MN : %a\n", Mn));\r
+ DEBUG ((DEBUG_INFO, " FR : 0x%lx\n", *((UINT64 *)ControllerData->Fr)));\r
DEBUG ((DEBUG_INFO, " RAB : 0x%x\n", ControllerData->Rab));\r
- DEBUG ((DEBUG_INFO, " IEEE : 0x%x\n", *(UINT32*)ControllerData->Ieee_oui));\r
+ DEBUG ((DEBUG_INFO, " IEEE : 0x%x\n", *(UINT32 *)ControllerData->Ieee_oui));\r
DEBUG ((DEBUG_INFO, " AERL : 0x%x\n", ControllerData->Aerl));\r
DEBUG ((DEBUG_INFO, " SQES : 0x%x\n", ControllerData->Sqes));\r
DEBUG ((DEBUG_INFO, " CQES : 0x%x\n", ControllerData->Cqes));\r
**/\r
EFI_STATUS\r
NvmeCreateIoCompletionQueue (\r
- IN PEI_NVME_CONTROLLER_PRIVATE_DATA *Private\r
+ IN PEI_NVME_CONTROLLER_PRIVATE_DATA *Private\r
)\r
{\r
- EFI_NVM_EXPRESS_PASS_THRU_COMMAND_PACKET CommandPacket;\r
- EFI_NVM_EXPRESS_COMMAND Command;\r
- EFI_NVM_EXPRESS_COMPLETION Completion;\r
- EFI_STATUS Status;\r
- NVME_ADMIN_CRIOCQ CrIoCq;\r
+ EFI_NVM_EXPRESS_PASS_THRU_COMMAND_PACKET CommandPacket;\r
+ EFI_NVM_EXPRESS_COMMAND Command;\r
+ EFI_NVM_EXPRESS_COMPLETION Completion;\r
+ EFI_STATUS Status;\r
+ NVME_ADMIN_CRIOCQ CrIoCq;\r
\r
- ZeroMem (&CommandPacket, sizeof(EFI_NVM_EXPRESS_PASS_THRU_COMMAND_PACKET));\r
- ZeroMem (&Command, sizeof(EFI_NVM_EXPRESS_COMMAND));\r
- ZeroMem (&Completion, sizeof(EFI_NVM_EXPRESS_COMPLETION));\r
- ZeroMem (&CrIoCq, sizeof(NVME_ADMIN_CRIOCQ));\r
+ ZeroMem (&CommandPacket, sizeof (EFI_NVM_EXPRESS_PASS_THRU_COMMAND_PACKET));\r
+ ZeroMem (&Command, sizeof (EFI_NVM_EXPRESS_COMMAND));\r
+ ZeroMem (&Completion, sizeof (EFI_NVM_EXPRESS_COMPLETION));\r
+ ZeroMem (&CrIoCq, sizeof (NVME_ADMIN_CRIOCQ));\r
\r
CommandPacket.NvmeCmd = &Command;\r
CommandPacket.NvmeCompletion = &Completion;\r
\r
- Command.Cdw0.Opcode = NVME_ADMIN_CRIOCQ_CMD;\r
+ Command.Cdw0.Opcode = NVME_ADMIN_CRIOCQ_CMD;\r
CommandPacket.TransferBuffer = Private->CqBuffer[NVME_IO_QUEUE];\r
CommandPacket.TransferLength = EFI_PAGE_SIZE;\r
CommandPacket.CommandTimeout = NVME_GENERIC_TIMEOUT;\r
**/\r
EFI_STATUS\r
NvmeCreateIoSubmissionQueue (\r
- IN PEI_NVME_CONTROLLER_PRIVATE_DATA *Private\r
+ IN PEI_NVME_CONTROLLER_PRIVATE_DATA *Private\r
)\r
{\r
- EFI_NVM_EXPRESS_PASS_THRU_COMMAND_PACKET CommandPacket;\r
- EFI_NVM_EXPRESS_COMMAND Command;\r
- EFI_NVM_EXPRESS_COMPLETION Completion;\r
- EFI_STATUS Status;\r
- NVME_ADMIN_CRIOSQ CrIoSq;\r
+ EFI_NVM_EXPRESS_PASS_THRU_COMMAND_PACKET CommandPacket;\r
+ EFI_NVM_EXPRESS_COMMAND Command;\r
+ EFI_NVM_EXPRESS_COMPLETION Completion;\r
+ EFI_STATUS Status;\r
+ NVME_ADMIN_CRIOSQ CrIoSq;\r
\r
- ZeroMem (&CommandPacket, sizeof(EFI_NVM_EXPRESS_PASS_THRU_COMMAND_PACKET));\r
- ZeroMem (&Command, sizeof(EFI_NVM_EXPRESS_COMMAND));\r
- ZeroMem (&Completion, sizeof(EFI_NVM_EXPRESS_COMPLETION));\r
- ZeroMem (&CrIoSq, sizeof(NVME_ADMIN_CRIOSQ));\r
+ ZeroMem (&CommandPacket, sizeof (EFI_NVM_EXPRESS_PASS_THRU_COMMAND_PACKET));\r
+ ZeroMem (&Command, sizeof (EFI_NVM_EXPRESS_COMMAND));\r
+ ZeroMem (&Completion, sizeof (EFI_NVM_EXPRESS_COMPLETION));\r
+ ZeroMem (&CrIoSq, sizeof (NVME_ADMIN_CRIOSQ));\r
\r
CommandPacket.NvmeCmd = &Command;\r
CommandPacket.NvmeCompletion = &Completion;\r
\r
- Command.Cdw0.Opcode = NVME_ADMIN_CRIOSQ_CMD;\r
+ Command.Cdw0.Opcode = NVME_ADMIN_CRIOSQ_CMD;\r
CommandPacket.TransferBuffer = Private->SqBuffer[NVME_IO_QUEUE];\r
CommandPacket.TransferLength = EFI_PAGE_SIZE;\r
CommandPacket.CommandTimeout = NVME_GENERIC_TIMEOUT;\r
**/\r
EFI_STATUS\r
NvmeControllerInit (\r
- IN PEI_NVME_CONTROLLER_PRIVATE_DATA *Private\r
+ IN PEI_NVME_CONTROLLER_PRIVATE_DATA *Private\r
)\r
{\r
- EFI_STATUS Status;\r
- UINTN Index;\r
- NVME_AQA Aqa;\r
- NVME_ASQ Asq;\r
- NVME_ACQ Acq;\r
- NVME_VER Ver;\r
+ EFI_STATUS Status;\r
+ UINTN Index;\r
+ NVME_AQA Aqa;\r
+ NVME_ASQ Asq;\r
+ NVME_ACQ Acq;\r
+ NVME_VER Ver;\r
\r
//\r
// Dump the NVME controller implementation version\r
ZeroMem ((VOID *)(UINTN)(&Private->SqTdbl[Index]), sizeof (NVME_SQTDBL));\r
ZeroMem ((VOID *)(UINTN)(&Private->CqHdbl[Index]), sizeof (NVME_CQHDBL));\r
}\r
+\r
ZeroMem (Private->Buffer, EFI_PAGE_SIZE * NVME_MEM_MAX_PAGES);\r
\r
//\r
return EFI_OUT_OF_RESOURCES;\r
}\r
}\r
+\r
Status = NvmeIdentifyController (Private, Private->ControllerData);\r
if (EFI_ERROR (Status)) {\r
DEBUG ((DEBUG_ERROR, "%a: NvmeIdentifyController fail, Status - %r\n", __FUNCTION__, Status));\r
return Status;\r
}\r
+\r
NvmeDumpControllerData (Private->ControllerData);\r
\r
//\r
DEBUG ((DEBUG_ERROR, "%a: Create IO completion queue fail, Status - %r\n", __FUNCTION__, Status));\r
return Status;\r
}\r
+\r
Status = NvmeCreateIoSubmissionQueue (Private);\r
if (EFI_ERROR (Status)) {\r
DEBUG ((DEBUG_ERROR, "%a: Create IO submission queue fail, Status - %r\n", __FUNCTION__, Status));\r
**/\r
VOID\r
NvmeFreeDmaResource (\r
- IN PEI_NVME_CONTROLLER_PRIVATE_DATA *Private\r
+ IN PEI_NVME_CONTROLLER_PRIVATE_DATA *Private\r
)\r
{\r
ASSERT (Private != NULL);\r
\r
if (Private->BufferMapping != NULL) {\r
IoMmuFreeBuffer (\r
- NVME_MEM_MAX_PAGES,\r
- Private->Buffer,\r
- Private->BufferMapping\r
- );\r
+ NVME_MEM_MAX_PAGES,\r
+ Private->Buffer,\r
+ Private->BufferMapping\r
+ );\r
}\r
\r
return;\r
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